公开(公告)号：EP0090590A2

公开(公告)日：1983-10-05

申请号：EP83301616.5

申请日：1983-03-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo Dai-2-Yayoi-so 5

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C8/00 ,  G11C8/18 ,  G11C11/419

摘要： A semiconductor memory device such as a static-type random-access memory device comprising an address-change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from a selected memory cell. The readout signal is input into the latch circuit in synchronization with the timing of the pulse signal or a short time after the pulse signal, and the readout data from the semiconductor memory device is obtained from the latch circuit, thereby increasing the time interval during which the readout data from the semiconductor memory device is available.

公开(公告)号：EP0090590B1

公开(公告)日：1987-03-04

申请号：EP83301616.5

申请日：1983-03-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo Dai-2-Yayoi-so 5

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C8/00 ,  G11C8/18 ,  G11C11/419