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公开(公告)号：EP0090738A3
公开(公告)日：1986-02-05
申请号：EP83400644
申请日：1983-03-29
申请人： FUJITSU LIMITED
IPC分类号： H01L27/02
CPC分类号： H01L21/74 , H01L21/743 , H01L27/0248
摘要： Electrostatical breakage of a semiconductor device comprising an epitaxial layer (106) and a buried layer (104) thereunder connected with an outer signal terminal (114-116) can be prevented by forming an impurity region (118) in the epitaxial layer so as to make a PN junction between the buried layer and the impurity region, the impurity region being connected with a power source or ground.
摘要翻译： 通过在外延层中形成杂质区（118），可以防止包括与外部信号端子（114-116）连接的外延层（106）和其下方的掩埋层（104）的半导体器件的静电破坏 在掩埋层和杂质区之间形成PN结，杂质区与电源或地连接。
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公开(公告)号：EP0090738A2
公开(公告)日：1983-10-05
申请号：EP83400644.7
申请日：1983-03-29
申请人： FUJITSU LIMITED
IPC分类号： H01L27/02
CPC分类号： H01L21/74 , H01L21/743 , H01L27/0248
摘要： Electrostatical breakage of a semiconductor device comprising an epitaxial layer (106) and a buried layer (104) thereunder connected with an outer signal terminal (114-116) can be prevented by forming an impurity region (118) in the epitaxial layer so as to make a PN junction between the buried layer and the impurity region, the impurity region being connected with a power source or ground.
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公开(公告)号：EP0090738B1
公开(公告)日：1989-07-12
申请号：EP83400644.7
申请日：1983-03-29
申请人： FUJITSU LIMITED
IPC分类号： H01L27/02
CPC分类号： H01L21/74 , H01L21/743 , H01L27/0248
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公开(公告)号：EP0121424B1
公开(公告)日：1990-01-31
申请号：EP84302183.3
申请日：1984-03-30
申请人： FUJITSU LIMITED
IPC分类号： H03K19/082 , H03K19/088 , H03K19/177 , H03K19/084 , H03K19/173
CPC分类号： H03K19/1778 , H01L27/11801 , H03K5/02 , H03K19/082 , H03K19/088 , H03K19/17796
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公开(公告)号：EP0121424A3
公开(公告)日：1987-02-04
申请号：EP84302183
申请日：1984-03-30
申请人： FUJITSU LIMITED
IPC分类号： H03K19/082 , H03K19/088 , H03K19/177
CPC分类号： H03K19/1778 , H01L27/11801 , H03K5/02 , H03K19/082 , H03K19/088 , H03K19/17796
摘要： A gate array LSI device having inner gate circuits whose performance is not affected by load capacitance at their output terminals and which have a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors (Q 6 - 1 ...Q 6 -m), each of which receives an input signal (IN 1 ... INm) atthe basethereof; a first NPN-typetransistor(Q 7 ) whose base is connected to the emitters of the PNP-type transistors; and an output buffer circuit including a second NPN-type transistor (Q 9 ), which is controlled by the emitter current of the first NPN-type transistor and which removes electric charge due to load capacitance from an output terminal, and a third NPN-type transistor (Q.) which is controlled by the collector cu rrent of the first NPN-type transistor and which is connected in series to the second NPN-type transistor so as to supply a charging current to the output terminal.
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公开(公告)号：EP0121424A2
公开(公告)日：1984-10-10
申请号：EP84302183.3
申请日：1984-03-30
申请人： FUJITSU LIMITED
IPC分类号： H03K19/082 , H03K19/088 , H03K19/177 , H03K19/084 , H03K19/173
CPC分类号： H03K19/1778 , H01L27/11801 , H03K5/02 , H03K19/082 , H03K19/088 , H03K19/17796
摘要： A gate array LSI device having inner gate circuits whose performance is not affected by load capacitance at their output terminals and which have a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors (Q 6 - 1 ...Q 6 -m), each of which receives an input signal (IN 1 ... INm) atthe basethereof; a first NPN-typetransistor(Q 7 ) whose base is connected to the emitters of the PNP-type transistors; and an output buffer circuit including a second NPN-type transistor (Q 9 ), which is controlled by the emitter current of the first NPN-type transistor and which removes electric charge due to load capacitance from an output terminal, and a third NPN-type transistor (Q.) which is controlled by the collector cu rrent of the first NPN-type transistor and which is connected in series to the second NPN-type transistor so as to supply a charging current to the output terminal.
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