公开(公告)号：EP0570597A1

公开(公告)日：1993-11-24

申请号：EP92924898.7

申请日：1992-12-09

申请人： FUJITSU LIMITED

发明人： AKAOGI, Takao Fujitsu Limited 1015, Kamikodanaka ,  KAWASHIMA, Hiromi Fujitsu Limited ,  TAKEGUCHI, Tetsuji Fujitsu Limited ,  HAGIWARA, Ryoji Fujitsu Limited ,  KASA, Yasushi Fujitsu Limited 1015, Kamikodanaka ,  ITANO, Kiyoshi Fujitsu Limited 1015, Kamikodanaka ,  OGAWA, Yasushige Fujitsu VLSI Limited ,  KAWAMURA, Shouichi Fujitsu Limited

IPC分类号： G11C16/06 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

摘要： A flash memory improved in its erasing operation by shortening its erasing time, wherein, when data is written prior to erasing, by selecting a plurality of lines of at least either of word lines and bit lines simultaneously, data is written into a plurality of transistors in concurrence.

摘要翻译： 闪存通过缩短擦除时间来改善其擦除操作，其中当通过同时选择字线和位线中的至少一个的数行时，在擦除之前写入数据时，将数据写入多个晶体管 同意。

公开(公告)号：EP0570597B1

公开(公告)日：2001-03-21

申请号：EP92924898.7

申请日：1992-12-09

申请人： FUJITSU LIMITED

发明人： AKAOGI, Takao Fujitsu Limited 1015, Kamikodanaka ,  KAWASHIMA, Hiromi Fujitsu Limited ,  TAKEGUCHI, Tetsuji Fujitsu Limited ,  HAGIWARA, Ryoji Fujitsu Limited ,  KASA, Yasushi Fujitsu Limited 1015, Kamikodanaka ,  ITANO, Kiyoshi Fujitsu Limited 1015, Kamikodanaka ,  OGAWA, Yasushige Fujitsu VLSI Limited ,  KAWAMURA, Shouichi Fujitsu Limited

IPC分类号： G11C16/06 ,  H03K19/21 ,  G11C5/14

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).