公开(公告)号：EP0163580A2

公开(公告)日：1985-12-04

申请号：EP85401065.9

申请日：1985-05-30

申请人： FUJITSU LIMITED

发明人： Nakano, Masao ,  Takemae, Yoshihiro ,  Nakano, Tomio ,  Tatematsu, Takeo Esuperansa Dai-3 ,  Ogawa, Junji ,  Horii, Takashi ,  Fujii, Yasuhiro ,  Sato, Kimiaki ,  Tsuge, Norihisa

IPC分类号： G06F11/20

CPC分类号： G11C29/835

摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit (24) for detecting coincidence between data read from the memory unit (21) and a received input address (Ao, An). Data produced from the comparison by the comparison unit is delivered through an external connection terminal (7).

公开(公告)号：EP0159928B1

公开(公告)日：1990-11-28

申请号：EP85400552.7

申请日：1985-03-22

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Tatematsu, Takeo Esuperansa Dai-3 ,  Tsuge, Norihisa ,  Ogawa, Junji ,  Horii, Takashi ,  Fujii, Yasuhiro ,  Nakano, Masao

IPC分类号： G11C17/00 ,  G06F11/20 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C8/10 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device connected between first and second voltage feet lines includes an information storing circuit (3) having a fuse (F) for storing information by blowing or not blowing the fuse, a voltage level conversion circuit (10) outputting a voltage (V min cc) lower than a voltage (Vcc) between the first and second voltage feed lines to the information storing circuit, and a circuit (5) connected between the first and second voltage feed lines, for outputting a detection signal (Si) in response to a voltage value at the fuse which is varied with the blown or unblown state of the fuse. The output voltage (V min cc) from the voltage level conversion circuit (10) is set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse, but higher than the threshold voltage of the information detection circuit (5). Said output voltage (V min cc) is at a predetermined value when the voltage between the first and second voltage feed lines is within a predetermined range, and increases in response to the increment of the voltage between the first and second voltage feed lines when said last mentioned voltage exceeds a predetermined range.

公开(公告)号：EP0163580B1

公开(公告)日：1996-09-04

申请号：EP85401065.9

申请日：1985-05-30

申请人： FUJITSU LIMITED

发明人： Nakano, Masao ,  Takemae, Yoshihiro ,  Nakano, Tomio ,  Tatematsu, Takeo Esuperansa Dai-3 ,  Ogawa, Junji ,  Horii, Takashi ,  Fujii, Yasuhiro ,  Sato, Kimiaki ,  Tsuge, Norihisa

IPC分类号： G06F11/20

CPC分类号： G11C29/835

摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

公开(公告)号：EP0159928A2

公开(公告)日：1985-10-30

申请号：EP85400552.7

申请日：1985-03-22

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Tatematsu, Takeo Esuperansa Dai-3 ,  Tsuge, Norihisa ,  Ogawa, Junji ,  Horii, Takashi ,  Fujii, Yasuhiro ,  Nakano, Masao

IPC分类号： G11C17/00 ,  G06F11/20 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C8/10 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device connected between first and second voltage feet lines includes an information storing circuit (3) having a fuse (F) for storing information by blowing or not blowing the fuse, a voltage level conversion circuit (10) outputting a voltage (V'cc) lower than a voltage (Vcc) between the first and second voltage feed lines to the information storing circuit, and a circuit (5) connected between the first and second voltage feed lines, for outputting a detection signal (S) in response to a voltage value at the fuse which is varied with the blown or unblown state of the fuse. The output voltage (V'cc) from the voltage level conversion circuit (10) is set as low as possible to restrain electromigration caused atthe vicinity of the blown portion of the fuse, but higher than the threshold voltage of the information detection circuit (5). Said output voltage (V'cc) is at a predetermined value when the voltage between the first and second voltage feed lines is within a predetermined range, and increases in response to the increment of the voltage between the first and second voltage feed lines when said last mentioned voltage exceeds a predetermined range.

摘要翻译： 连接在第一和第二电压脚线之间的半导体集成电路装置包括：信息存储电路（3），具有用于通过吹送或不熔断熔丝来存储信息的熔丝（F）;输出电压的电压电平转换电路（10） 低于第一和第二电压馈送线之间的电压（Vcc）的信号存储电路;以及电路（5），连接在第一和第二电压馈送线之间，用于输出检测信号 对熔断器的电压值进行响应，该电压值随保险丝的熔断状态或未熔断状态而变化。 来自电压电平转换电路（10）的输出电压（V min cc）被设置为尽可能低以抑制在熔丝的熔断部分附近引起的电迁移但高于信息检测电路（的阈值电压 5）。 当所述第一和第二电压馈电线之间的电压在预定范围内时，所述输出电压（V min cc）为预定值，并且响应于所述第一和第二电压馈电线之间的电压的增加而增加 最后提到的电压超过预定范围。