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    PREFETCH REQUEST CIRCUIT
    3.
    发明公开
    PREFETCH REQUEST CIRCUIT 有权
    VORABRUF-ANFORDERUNGSSCHALTUNG

    公开(公告)号：EP2416250A1

    公开(公告)日：2012-02-08

    申请号：EP09842915.2

    申请日：2009-03-30

    申请人： Fujitsu Limited

    发明人： FUSEJIMA, Atsushi ,  GOMYO, Norihito

    IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F12/02 ,  G06F12/04

    CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/34 ,  G06F9/383

    摘要： When a state in which respective instruction flows corresponding to a memory copy instruction specifying data copy or move between memory addresses are executed with a maximum specifiable data transfer volume is specified by +P_MVC_256_1ST signal, 1-bit latch 703 holds the state during the period of multi-flow expansion specified by +D_MF_TGR signal. An AND circuit 705 ANDs an output signal of the 1-bit latch 703 and +P_EAG_VALID signal indicating the execution timing of the respective instruction flows, and outputs a prefetch request signal +P_PREFETCH_REQUEST via an OR circuit 706 every time when the instruction flow is issued.

    摘要翻译： 当通过+ P_MVC_256_1ST信号指定与指定数据复制或存储器地址之间移动的存储器复制指令相对应的指令流以最大可指定数据传送量执行的状态时，1位锁存器703保持在 由+ D_MF_TGR信号指定的多流量扩展。 AND电路705对1位锁存器703的输出信号和表示各个指令流的执行定时的+ P_EAG_VALID信号进行AND分配，并且每当发出指令流时经由或电路706输出预取请求信号+ P_PREFETCH_REQUEST 。

    PROCESSOR
    4.
    发明公开
    PROCESSOR 有权
    处理器

    公开(公告)号：EP2159685A1

    公开(公告)日：2010-03-03

    申请号：EP07767283.0

    申请日：2007-06-20

    申请人： Fujitsu Limited

    发明人： FUSEJIMA, Atsushi ,  SUZUKI, Takashi ,  YOSHIDA, Toshio ,  AKIZUKI, Yasunobu

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3851 ,  G06F9/3013 ,  G06F9/3857 ,  G06F11/3466 ,  G06F2201/88

    摘要： A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.

    摘要翻译： 处理单元包括多个线程执行单元，每个线程执行单元设置有性能分析电路，用于测量由执行指令产生的各种类型的事件，以及提交堆栈输入单元，用于控制已执行指令的完成，并且每个执行具有多个 指令;提交范围寄存器，用于通过由每个线程执行单元执行来存储存储在每个提交堆栈入口单元中的完成候选指令，并且执行用于完成包含在该线程中的指令的处理;以及线程选择装置，用于发送指令的提交事件 在对提交范围寄存器中存储的指令进行提交处理时，向与指令对应的每个线程执行单元中提供的性能分析电路。