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公开(公告)号:EP4243080A3
公开(公告)日:2023-11-08
申请号:EP23185430.8
申请日:2013-11-18
发明人: ARTHUR, Stephen Daley , MATOCHA, Kevin Sean , RAO, Ramakrishna , LOSEE, Peter, Almern , BOLOTNIKOV, Alexander Viktorovich
IPC分类号: H01L29/78 , H01L29/423 , H01L21/336 , H01L29/66 , H03K17/687 , H01L29/16
摘要: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.
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公开(公告)号:EP4243080A2
公开(公告)日:2023-09-13
申请号:EP23185430.8
申请日:2013-11-18
发明人: ARTHUR, Stephen Daley , MATOCHA, Kevin Sean , RAO, Ramakrishna , LOSEE, Peter, Almern , BOLOTNIKOV, Alexander Viktorovich
IPC分类号: H01L29/16
摘要: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.
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