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    ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING
    2.
    发明公开
    ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING 审中-公开

    公开(公告)号：EP3852050A1

    公开(公告)日：2021-07-21

    申请号：EP21159716.6

    申请日：2016-04-06

    申请人： Google LLC

    发明人： ZHU, Qiuling ,  SHACHAM, Ofer ,  MEIXNER, Albert ,  REDGRAVE, Jason Rupert ,  FINCHELSTEIN, Daniel Frederic ,  PATTERSON, David ,  DESAI, Neeti ,  STARK, Donald ,  CHANG, Edward T. ,  MARK, William R.

    IPC分类号： G06T1/60 ,  G06T1/20

    摘要： An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.