公开(公告)号：EP2793461A4

公开(公告)日：2015-08-26

申请号：EP12857222

申请日：2012-05-29

申请人： HANGZHOU HIKVISION DIGITAL TEC

发明人： SHI ENYI ,  HUANG TIAN ,  QIAN XUEFENG

IPC分类号： H04N7/08 ,  G06F3/14 ,  G09G5/399

CPC分类号： G06F3/1446 ,  G06F3/1438 ,  G06T1/20 ,  G09G5/393 ,  G09G5/399 ,  H04N5/04 ,  H04N5/265

摘要： The present invention relates to the field of video processing. Disclosed are a multi-processor video processing system and video image synchronous transmission and display method therein. Via PCIE bus technology, synchronous transmission and tiled display of video image in the multi-CPU system is implemented. In the present invention, the multi-processor system includes multiple processors that are connected via a PCIE bus and each comprises a display unit and a decoding unit; a memory area of the display unit comprises two buffers, a read information packet containing a read flag, and a write information packet containing a write flag. The method includes the following steps: a decoding unit generating a frame of uncompressed image, performing the following steps on each corresponding display unit: if the read and write flags corresponding to the display unit are equal, sending, by calling the PCIE bus or using local transmission, the image to an idle buffer indicated by the write flag, and negating the write flag; each display unit querying for corresponding read and write flags according to a display refresh frequency; if the read and write flags are not equal, using the buffer indicated by the read flag as a storage area for data to be displayed next time, and setting the read flag to a write flag value.

摘要翻译： 本发明涉及视频处理的领域。 本发明公开了一种多处理器的视频处理系统及所视频图像同步传输和显示方法。 通过PCIe总线技术，同步传输，并在多CPU系统的视频图像的拼接显示被实现。 另外，在本发明中，多处理器系统包括多个处理器并经由PCIE总线连接，并且每个包括显示单元和解码单元; 所述显示单元的一个存储区域包括两个缓冲器，读出信息包含一个读取的标志，和包含写标记的写入信息包。 该方法包括以下步骤：解码单元，生成未压缩的图像的帧，执行每个相应的显示单元上执行以下步骤：如果读出和写入的标志对应于所述显示单元是相等的，发送，通过调用PCIE总线或使用 本地传输，在由写标志，并且否定写入标志指示的闲置缓冲器中的图像来; 每一个显示单元中查询对应gemäß到显示器刷新频率读写标志; 如果读写标志不相等，使用由该读标志指示为要显示的数据下一次的存储区域的缓冲液，并将所读取的标记设置到写入标志值。