利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.014 秒)

    Processor capable of executing one or more programs by a plurality of operation units
    3.
    发明公开
    Processor capable of executing one or more programs by a plurality of operation units 失效
    用一个或多个程序的能力执行具有多个功能单元的处理单元。

    公开(公告)号：EP0180227A2

    公开(公告)日：1986-05-07

    申请号：EP85113878.4

    申请日：1985-10-31

    申请人： HITACHI, LTD.

    发明人： Ueda, Hirotada ,  Matsushima, Hitoshi ,  Hagiwara, Yoshimune ,  Kaneko, Kenji

    IPC分类号： G06F9/28

    CPC分类号： G06F9/28 ,  G06F9/3885

    摘要： A processor comprises first and second operation units (1, 2), a first program memory (3) which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory (4) which contains microinstructions for controlling the second operation unit, first control means (7) connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means (8) connected to the second program memory for controlling the second operation unit.
    In a normal mode, all operation units (1, 2) are under control of the first control means (7) and in a multi-program mode, the first operation unit (1) is under control of the first control means (7) and the second operation unit (2) is under control of the second control means (8). These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories (3.4).

    Method and apparatus for recording/reproducing image information on/from removable medium
    5.
    发明公开
    Method and apparatus for recording/reproducing image information on/from removable medium 有权
    用于记录/再现图像上/从可移动介质中的信息的方法和装置

    公开(公告)号：EP1089276A2

    公开(公告)日：2001-04-04

    申请号：EP00120114.4

    申请日：2000-09-19

    申请人： HITACHI DENSHI KABUSHIKI KAISHA ,  Hitachi, Ltd.

    发明人： Takada, Tomomi ,  Ueda, Hirotada ,  Hirai, Seiichi ,  Kageyama, Masahiro ,  Tanabe, Hisao

    IPC分类号： G11B20/18 ,  G11B20/10

    CPC分类号： G11B27/329 ,  G11B20/10527 ,  G11B20/18 ,  G11B27/105 ,  G11B2220/216 ,  G11B2220/2562 ,  G11B2220/2575 ,  H04N5/77 ,  H04N5/85

    摘要： In an image recording/reproduction method for recording image information on a recording medium by using a computer, a verify mode is set into the OFF state (506) when recording image information on said recording medium. In addition, use as a write or read region a specified region of the recording medium which is greater than or equal to a unitary data size being handled during error correction processing to be performed when writing or reading image information on or out of said recording medium. Additionally, upon reading of image information from the recording medium, any image information that has experienced read errors will never be read again.

    摘要翻译： 在用于通过使用计算机记录在记录介质上的图像信息的图像记录/再现方法中，验证模式被设置成断开状态（506）的记录，当所述记录介质上的图像信息。 另外，使用作为写或读出区的记录介质的所有其是大于或等于一个单一数据大小的纠错处理过程中被处理写入或读或缩小所述记录介质的图像信息时执行的指定区域 ， 此外，在从记录介质的图像信息的读取，图像的任何信息都已经经历读取错误再也不会被读取。

    Parallel data processing system
    7.
    发明公开
    Parallel data processing system 失效
    平行机Datenverarbeitungssystem。

    公开(公告)号：EP0147857A2

    公开(公告)日：1985-07-10

    申请号：EP84116392.6

    申请日：1984-12-27

    申请人： HITACHI, LTD.

    发明人： Matsushima, Hitoshi ,  Ueda, Hirotada

    IPC分类号： G06F15/66 ,  G06F15/76 ,  G06F15/16 ,  G06F15/62

    CPC分类号： G06T1/20 ,  G06F15/8015

    摘要： A parallel data processing system comprising a control means (3-11, a plurality of processing means (3-2) controlled by said control means and adapted to perform parallel data processing, memory means provided correspondingly to said processing means and adapted to store data for corresponding processing means, and ring bus means (3-3) connecting said memory means in a ring configuration so that data is shifted along the ring bus. Each of the processing means performs data processing based on data transferred to the corresponding memory means.

    摘要翻译： 一种并行数据处理系统，包括控制装置（3-1），由所述控制装置控制并适于执行并行数据处理的多个处理装置（3-2），与所述处理装置相对应地设置的存储装置， 相应处理装置的数据以及以环形结构连接所述存储装置的环形总线装置（3-3），使得数据沿着环形总线移位。 每个处理装置基于传送到相应存储装置的数据执行数据处理。

    Multiprocessor system
    8.
    发明公开
    Multiprocessor system 失效
    Multiprozessorsystem。

    公开(公告)号：EP0236762A1

    公开(公告)日：1987-09-16

    申请号：EP87101820.6

    申请日：1987-02-10

    申请人： HITACHI, LTD.

    发明人： Ueda, Hirotada ,  Kato, Kanji ,  Matsushima, Hitoshi

    IPC分类号： G06F15/66 ,  G06F15/16

    CPC分类号： G06F15/8015 ,  G06T1/20

    摘要： A multiprocessor system includes processor units (20) connected physically in one-dimensional fashion along a ring bus (1) located at the node of each processor element (3) and associated local memory (2), so that various system operating modes are possible. The ring bus is used for inter-processor data transfer, with the address and read/write signals to each local memory being supplied from the processor element (by the program). Synchronization between the data flow on the ring bus and the processor operation is made automatic by the innovated method of inter-processor connection, which includes flag latches in the ring bus, whereby the system accomplishes extremely high-speed processing.

    Processor capable of executing one or more programs by a plurality of operation units
    10.
    发明公开
    Processor capable of executing one or more programs by a plurality of operation units 失效
    能够由多个操作单位执行一个或多个程序的处理人员

    公开(公告)号：EP0180227A3

    公开(公告)日：1990-11-14

    申请号：EP85113878.4

    申请日：1985-10-31

    申请人： HITACHI, LTD.

    发明人： Ueda, Hirotada ,  Matsushima, Hitoshi ,  Hagiwara, Yoshimune ,  Kaneko, Kenji

    IPC分类号： G06F9/28

    CPC分类号： G06F9/28 ,  G06F9/3885

    摘要： A processor comprises first and second operation units (1, 2), a first program memory (3) which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory (4) which contains microinstructions for controlling the second operation unit, first control means (7) connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means (8) connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units (1, 2) are under control of the first control means (7) and in a multi-program mode, the first operation unit (1) is under control of the first control means (7) and the second operation unit (2) is under control of the second control means (8). These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories (3.4).