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公开(公告)号：EP0502436B1
公开(公告)日：1997-05-02
申请号：EP92103448.4
申请日：1992-02-28
申请人： HITACHI, LTD.
发明人： Kozaki, Takahiko , Yanagi, Junichirou , Aiki, Kiyoshi , Ito, Yutaka , Aoki, Kaoru , Gohara, Shinobu
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L49/108 , H04L49/203 , H04L49/255 , H04L2012/5638 , H04L2012/5672 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
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公开(公告)号：EP0502436A3
公开(公告)日：1992-10-14
申请号：EP92103448.4
申请日：1992-02-28
申请人： HITACHI, LTD.
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L49/108 , H04L49/203 , H04L49/255 , H04L2012/5638 , H04L2012/5672 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
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公开(公告)号：EP0471344A1
公开(公告)日：1992-02-19
申请号：EP91113586.1
申请日：1991-08-13
申请人： HITACHI, LTD.
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/255 , H04L49/3081 , H04L2012/568 , H04Q11/0478
摘要： A traffic shaping method and circuit of a packet switching system in which input packets having a fixed length and multiplexed on a plurality of inputs (501-1...501-36) are multiplexed (11) to be delivered on any one of a plurality of outputs (502-1...502-36), connects the input packet to list structure using an address chain formed for each output, forms the list structure even for each line identifier provided in the packet, and assigns the identifier for each time slot of the output to take out the packet from the list structure, to prevent packets having the same identifier from being multiplexed and delivered to the output continuously.
摘要翻译： 一种分组交换系统的流量整形方法和电路，其中具有固定长度并被复用在多个输入（501-1 ... 501-36）上的输入分组被多路复用（11），以在 多个输出（502-1 ... 502-36）使用为每个输出形成的地址链将输入分组连接到列表结构，即使对于分组中提供的每一行标识符也构成列表结构，并且为 输出的每个时隙从列表结构中取出分组，以防止具有相同标识符的分组被多路复用并连续传送到输出。
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公开(公告)号：EP0471344B1
公开(公告)日：1997-02-12
申请号：EP91113586.1
申请日：1991-08-13
申请人： HITACHI, LTD.
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/255 , H04L49/3081 , H04L2012/568 , H04Q11/0478
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公开(公告)号：EP0502436A2
公开(公告)日：1992-09-09
申请号：EP92103448.4
申请日：1992-02-28
申请人： HITACHI, LTD.
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L49/108 , H04L49/203 , H04L49/255 , H04L2012/5638 , H04L2012/5672 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
摘要翻译： ATM交换系统包括具有多个输入端口和具有相同小区传输速率的多个输出端口的交换单元，以及多路复用器，用于将从至少两个输出端口输出的单元列多路复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于将单元列从输出端口分解成多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之间分配 循环，以及用于通过共享缓冲存储器控制单元的写入和读取操作的缓冲存储器控制电路。 缓冲存储器控制电路具有控制表装置，用于输出要从共享缓冲存储器读取的单元输出的输出行的标识符，并且从由控制器输出的输出行标识符指定的链中读取单元 桌面设备
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