公开(公告)号：EP0453268A2

公开(公告)日：1991-10-23

申请号：EP91303435.1

申请日：1991-04-17

申请人： HITACHI, LTD. ,  HITACHI MICROCOMPUTER SYSTEM LTD.

发明人： Matsui, Shigezumi ,  Kawasaki, Ikuya ,  Kondo, Yoshiyuki ,  Hashimoto, Kouji

IPC分类号： G06F11/00

CPC分类号： G06F11/364 ,  G06F11/261 ,  G06F11/34 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3652

摘要： A microprocessor having a buffer (10) or memory capable of holding a plurality of instructions in advance has a function to permitting the insertion of a special bus cycle for outputting the internal information of the microprocessor externally of the microprocessor in a predetermined operation mode at the time of each execution. The information inside the microprocessor, which is to be outputted to the exterior in the special bus cycle, is exemplified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In the emulation of the system using the instruction prefetch type microprocessor, according to the means described above, the instruction that has been executed can be easily known from the exterior so that an accurate emulation analysis is possible and facilitating the analysis of the trace data thereby to improve the debugging efficiency.

摘要翻译： 具有缓冲器（10）或能够预先保持多个指令的存储器的微处理器具有允许插入专用总线周期，以在预定的操作模式下以微处理器的外部输出微处理器的内部信息 每次执行的时间 要在特殊总线周期中输出到外部的微处理器内的信息通过存储空间中执行的指令的地址，指令代码或用于在预取的指令组中识别所述执行的指令的代码 。 在使用指令预取型微处理器的系统的仿真中，根据上述手段，可以从外部容易地知道执行的指令，从而可以进行精确的仿真分析，并且便于对跟踪数据进行分析 提高调试效率。

公开(公告)号：EP0453268B1

公开(公告)日：1997-10-22

申请号：EP91303435.1

申请日：1991-04-17

申请人： HITACHI, LTD. ,  HITACHI MICROCOMPUTER SYSTEM LTD.

发明人： Matsui, Shigezumi ,  Kawasaki, Ikuya ,  Kondo, Yoshiyuki ,  Hashimoto, Kouji

IPC分类号： G06F11/00

CPC分类号： G06F11/364 ,  G06F11/261 ,  G06F11/34 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3652

公开(公告)号：EP0453268A3

公开(公告)日：1992-10-14

申请号：EP91303435.1

申请日：1991-04-17

申请人： HITACHI, LTD. ,  HITACHI MICROCOMPUTER SYSTEM LTD.

发明人： Matsui, Shigezumi ,  Kawasaki, Ikuya ,  Kondo, Yoshiyuki ,  Hashimoto, Kouji

IPC分类号： G06F11/00

CPC分类号： G06F11/364 ,  G06F11/261 ,  G06F11/34 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3652

摘要： A microprocessor having a buffer (10) or memory capable of holding a plurality of instructions in advance has a function to permitting the insertion of a special bus cycle for outputting the internal information of the microprocessor externally of the microprocessor in a predetermined operation mode at the time of each execution. The information inside the microprocessor, which is to be outputted to the exterior in the special bus cycle, is exemplified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In the emulation of the system using the instruction prefetch type microprocessor, according to the means described above, the instruction that has been executed can be easily known from the exterior so that an accurate emulation analysis is possible and facilitating the analysis of the trace data thereby to improve the debugging efficiency.

公开(公告)号：EP0591753A2

公开(公告)日：1994-04-13

申请号：EP93115196.3

申请日：1993-09-21

申请人： HITACHI, LTD.

发明人： Yoshioka, Shinichi ,  Kondo, Yoshiyuki ,  Takagi, Katsuaki

IPC分类号： G06F11/00

CPC分类号： G06F11/3652

摘要： The data processor 1 has a mode in which instructions are executed one module at a time, the module being a subroutine of high-level language, and a break is activated immediately after executing a return instruction at the end of the module. This mode is set in the control register (MSCNT) by an emulator. In this mode, a return address, the address to which the processing returns from the subroutine, is saved in the return address hold register (RAH) by using a return address which is stacked at a time of executing a branch instruction. The return address saved in the return address hold register (RAH) is compared by the comparator circuit 52 with the return address which is popped up from the stack into the instruction pointer (IP) at the execution of the return instruction at the end of the subroutine. When they agree, a break is activated.

摘要翻译： 数据处理器1具有一次一个模块执行指令的模式，该模块是高级语言的子程序，并且在执行模块末尾的返回指令之后立即启动中断。 该模式由仿真器在控制寄存器（MSCNT）中设置。 在该模式中，通过使用在执行分支指令时堆叠的返回地址，返回地址（从子程序返回的处理地址）保存在返回地址保持寄存器（RAH）中。 保存在返回地址保持寄存器（RAH）中的返回地址由比较器电路52与返回地址进行比较，该返回地址在执行返回指令结束时从堆栈弹出到指令指针（IP）中 子程序。 当他们同意时，休息被激活。

公开(公告)号：EP0591753A3

公开(公告)日：1994-08-03

申请号：EP93115196.3

申请日：1993-09-21

申请人： HITACHI, LTD.

发明人： Yoshioka, Shinichi ,  Kondo, Yoshiyuki ,  Takagi, Katsuaki

IPC分类号： G06F11/00

CPC分类号： G06F11/3652

摘要： The data processor 1 has a mode in which instructions are executed one module at a time, the module being a subroutine of high-level language, and a break is activated immediately after executing a return instruction at the end of the module. This mode is set in the control register (MSCNT) by an emulator. In this mode, a return address, the address to which the processing returns from the subroutine, is saved in the return address hold register (RAH) by using a return address which is stacked at a time of executing a branch instruction. The return address saved in the return address hold register (RAH) is compared by the comparator circuit 52 with the return address which is popped up from the stack into the instruction pointer (IP) at the execution of the return instruction at the end of the subroutine. When they agree, a break is activated.

摘要翻译： 数据处理器1具有一次执行一个模块的指令的模式，该模块是高级语言的子程序，并且在模块结束处执行返回指令之后立即激活中断。 该模式由仿真器在控制寄存器（MSCNT）中设置。 在这种模式下，通过使用执行分支指令时堆叠的返回地址，将返回地址（处理从子例程返回到的地址）保存在返回地址保持寄存器（RAH）中。 保存在返回地址保持寄存器（RAH）中的返回地址由比较器电路52与在执行返回指令时从堆栈弹出到指令指针（IP）中的返回地址进行比较 子程序。 当他们同意时，休息被激活。