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8 条记录 (耗时 0.012 秒)

    Wobble signal detecting circuit, wobble abnormality detecting circuit, information processing apparatus using these circuits and method, and recording medium used in the apparatus or method
    2.
    发明公开
    Wobble signal detecting circuit, wobble abnormality detecting circuit, information processing apparatus using these circuits and method, and recording medium used in the apparatus or method 失效
    摆动信号检测电路，摆动异常检测电路，使用这些电路的信息处理装置和方法以及在该装置或方法中使用的记录介质

    公开(公告)号：EP0866455A2

    公开(公告)日：1998-09-23

    申请号：EP98104169.2

    申请日：1998-03-09

    申请人： Hitachi, Ltd.

    发明人： Fushimi, Tetsuya ,  Kaku, Toshimitsu ,  Ikeda, Tetsuya ,  Ishibashi, Toshiaki, 201, Haitsu-yoshihara ,  Shigematsu, Kazuo

    IPC分类号： G11B20/10 ,  G11B27/30 ,  G11B27/19 ,  G11B7/00

    CPC分类号： G11B27/3027 ,  G11B7/00375 ,  G11B7/24082 ,  G11B7/24085 ,  G11B20/10 ,  G11B20/1217 ,  G11B20/1258 ,  G11B20/1403 ,  G11B27/19

    摘要： In a wobble signal detecting circuit provided by the present invention, a wobble signal is converted into binary data before being supplied to a PLL circuit by way of a polarity switching circuit and a clock switching circuit. The PLL circuit outputs a recording/playback timing generation clock signal. The frequency of the recording/playback timing generation clock signal is divided by a frequency dividing circuit before being fed back to the PLL circuit. A difference in phase between the wobble signal and the feedback signal is detected by a phase inversion detecting circuit and, if the difference in phase exceeds a phase difference determined in advance, the phase inversion detecting circuit generates a polarity switching signal for switching the polarity of the wobble signal. The polarity switching signal is used to invert the polarity of the polarity switching circuit.

    摘要翻译： 在本发明提供的摆动信号检测电路中，摆动信号在通过极性转换电路和时钟转换电路提供给PLL电路之前转换成二进制数据。 PLL电路输出记录/重放定时生成时钟信号。 记录/重放定时产生时钟信号的频率在被反馈到PLL电路之前被分频电路分频。 摆动信号和反馈信号之间的相位差由相位反转检测电路检测，并且如果相位差超过预先确定的相位差，则相位反转检测电路产生极性转换信号，用于转换极性 摆动信号。 极性切换信号用于反转极性切换电路的极性。

    Character and pattern display system
    5.
    发明公开
    Character and pattern display system 失效
    显示系统的字符和图案。

    公开(公告)号：EP0167802A2

    公开(公告)日：1986-01-15

    申请号：EP85106814.8

    申请日：1985-06-03

    申请人： HITACHI, LTD.

    发明人： Ikeda, Tetsuya

    IPC分类号： G09G1/28

    CPC分类号： G09G5/06

    摘要： A character and pattern display system having display memories (12) composed of memory planes (12r, 12g, 12b) for storing red, green and blue data, comprises a color data register (13) in which foreground color and background color data are set, and a pattern data select and control circuit (15) which, in response to an output from the color data register (13), converts pattern data into data to be written into the memory planes (12r, 12g, 12b).
    In writing character and pattern data of designated foreground colors and background colors into the memory planes of red, green and blue, the processing is raised in speed.

    Character and pattern display system
    6.
    发明公开
    Character and pattern display system 失效
    字符和图案显示系统

    公开(公告)号：EP0167802A3

    公开(公告)日：1989-06-14

    申请号：EP85106814.8

    申请日：1985-06-03

    申请人： HITACHI, LTD.

    发明人： Ikeda, Tetsuya

    IPC分类号： G09G1/28

    CPC分类号： G09G5/06

    摘要： A character and pattern display system having display memories (12) composed of memory planes (12r, 12g, 12b) for storing red, green and blue data, comprises a color data register (13) in which foreground color and background color data are set, and a pattern data select and control circuit (15) which, in response to an output from the color data register (13), converts pattern data into data to be written into the memory planes (12r, 12g, 12b). In writing character and pattern data of designated foreground colors and background colors into the memory planes of red, green and blue, the processing is raised in speed.

    Image display memory unit
    7.
    发明公开
    Image display memory unit 失效
    图像显示存储单元

    公开(公告)号：EP0093954A3

    公开(公告)日：1984-10-03

    申请号：EP83104112

    申请日：1983-04-27

    申请人： HITACHI, LTD.

    发明人： Ikeda, Tetsuya ,  Komatsu, Shigeru ,  Hirahata, Shigeru ,  Koyama, Tokuo

    IPC分类号： G09G01/28

    CPC分类号： G09G5/022

    摘要： An image display memory unit having a plurality of display memories (6, 7, 8) connected to a plurality of data lines of data bus (3) one for each display memory chip and addressable for each bit of the data bus comprises a display memory chip selection circuit (13) for selecting the display memory chip for each data bit on the same address, and a write control circuit (16, 17, 18) for controlling writing for each display memory. The dot-by-dot coloring is attained only by a software processing of controlling write information for each display memory and selecting the display memory chip.

    Image display memory unit
    8.
    发明公开
    Image display memory unit 失效
    Bildanzeigespeicher。

    公开(公告)号：EP0093954A2

    公开(公告)日：1983-11-16

    申请号：EP83104112.4

    申请日：1983-04-27

    申请人： HITACHI, LTD.

    发明人： Ikeda, Tetsuya ,  Komatsu, Shigeru ,  Hirahata, Shigeru ,  Koyama, Tokuo

    IPC分类号： G09G1/28

    CPC分类号： G09G5/022

    摘要： An image display memory unit having a plurality of display memories (6, 7, 8) connected to a plurality of data lines of data bus (3) one for each display memory chip and addressable for each bit of the data bus comprises a display memory chip selection circuit (13) for selecting the display memory chip for each data bit on the same address, and a write control circuit (16, 17, 18) for controlling writing for each display memory. The dot-by-dot coloring is attained only by a software processing of controlling write information for each display memory and selecting the display memory chip.

    摘要翻译： 具有连接到数据总线（3）的多个数据线的多个显示存储器（6,7,8）的图像显示存储器单元，每个显示存储器芯片一个用于每个显示存储器芯片并且可寻址数据总线的每一位包括显示存储器 用于对同一地址上的每个数据位选择显示存储器芯片的芯片选择电路（13），以及用于控制每个显示存储器的写入的写入控制电路（16,17,18）。 逐点着色仅通过控制每个显示存储器的写入信息和选择显示存储器芯片的软件处理来实现。