公开(公告)号：EP0076494A3

公开(公告)日：1983-05-18

申请号：EP82109102

申请日：1982-10-01

申请人： Hitachi, Ltd.

发明人： Takakura, Mitsuro ,  Shimoyama, Kazuhiko ,  Okamoto, Tadashi ,  Azusawa, Noboru ,  Yoshida, Takenari ,  Saito, Yutaka ,  Sakurai, Takakazu ,  Kitani, Susumu ,  Kikuchi, Yuji ,  Kamigane, Yoshihiro

IPC分类号： G06F03/04 ,  G06F15/16

CPC分类号： G06F15/161 ,  G06F13/366

摘要： A data transmission system for transferring data between a plurality of processors (200A - 200G, 200Z, 2000) and between the processors and an input/output unit (303) through a common bus (301) has linkage units (300A - 300G, 300Z, 300L) between the processors and the bus and an address controller (302) to manage the bus. Each of the linkage units has a two-port random access memory (42A - 42G) for storing data necessary for the processor. The processor processes the data stored in the memory and writes a result of the processing in an output area of the memory. The processing of the processors and the data transfer through the bus are essentially separated and carried out independently.

公开(公告)号：EP0076494B1

公开(公告)日：1988-08-24

申请号：EP82109102.2

申请日：1982-10-01

申请人： Hitachi, Ltd.

发明人： Takakura, Mitsuro ,  Shimoyama, Kazuhiko ,  Okamoto, Tadashi ,  Azusawa, Noboru ,  Yoshida, Takenari ,  Saito, Yutaka ,  Sakurai, Takakazu ,  Kitani, Susumu ,  Kikuchi, Yuji ,  Kamigane, Yoshihiro

IPC分类号： G06F13/00 ,  G06F15/16

CPC分类号： G06F15/161 ,  G06F13/366

公开(公告)号：EP0076494A2

公开(公告)日：1983-04-13

申请号：EP82109102.2

申请日：1982-10-01

申请人： Hitachi, Ltd.

发明人： Takakura, Mitsuro ,  Shimoyama, Kazuhiko ,  Okamoto, Tadashi ,  Azusawa, Noboru ,  Yoshida, Takenari ,  Saito, Yutaka ,  Sakurai, Takakazu ,  Kitani, Susumu ,  Kikuchi, Yuji ,  Kamigane, Yoshihiro

IPC分类号： G06F13/00 ,  G06F15/16

CPC分类号： G06F15/161 ,  G06F13/366

摘要： A data transmission system for transferring data between a plurality of processors (200A - 200G, 200Z, 2000) and between the processors and an input/output unit (303) through a common bus (301) has linkage units (300A - 300G, 300Z, 300L) between the processors and the bus and an address controller (302) to manage the bus. Each of the linkage units has a two-port random access memory (42A - 42G) for storing data necessary for the processor. The processor processes the data stored in the memory and writes a result of the processing in an output area of the memory. The processing of the processors and the data transfer through the bus are essentially separated and carried out independently.

摘要翻译： 用于通过公共总线（301）在多个处理器（200A-200G，200Z，2000）之间以及处理器与输入/输出单元（303）之间传送数据的数据传输系统具有连接单元（300A-300G，300Z ，300L）和地址控制器（302）之间，用于管理总线。 每个联动单元具有用于存储处理器所需的数据的双端口随机存取存储器（42A-42G）。 处理器处理存储在存储器中的数据，并将处理结果写入存储器的输出区域。 处理器的处理和通过总线的数据传输基本上是分开的，并且是独立执行的。