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公开(公告)号：EP3241288B1
公开(公告)日：2018-06-06
申请号：EP15828805.0
申请日：2015-12-29
IPC分类号： H04B7/185
CPC分类号： H04L27/22 , H03M1/12 , H04B7/18517 , H04L27/345
摘要： Systems and methods provide a receiver design capable of both wideband (high symbol rate) and narrowband (low symbol rate) operations requirements without compromising narrowband performance. Moreover, such a receiver design can be very low cost, and eschewing the need for any expensive and/or specialized elements. A receiver configured in accordance with various embodiments utilizes a fully integrated tuner in which narrowband filters are configured to be bypassable when in wideband (high symbol rate) mode in favor of fixed wideband filters. Additionally, an analog-to-digital converter (ADC) can be implemented with digital gain for wideband operation, as well as digital data bit mapping to accommodate industry standard application-specific integrated circuits (ASICs) interfaces, such as from a 12 bit ADC core to an 8 bit digital interface.
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公开(公告)号：EP3241288A1
公开(公告)日：2017-11-08
申请号：EP15828805.0
申请日：2015-12-29
IPC分类号： H04B7/185
CPC分类号： H04L27/22 , H03M1/12 , H04B7/18517 , H04L27/345
摘要： Systems and methods provide a receiver design capable of both wideband (high symbol rate) and narrowband (low symbol rate) operations requirements without compromising narrowband performance. Moreover, such a receiver design can be very low cost, and eschewing the need for any expensive and/or specialized elements. A receiver configured in accordance with various embodiments utilizes a fully integrated tuner in which narrowband filters are configured to be bypassable when in wideband (high symbol rate) mode in favor of fixed wideband filters. Additionally, an analog-to-digital converter (ADC) can be implemented with digital gain for wideband operation, as well as digital data bit mapping to accommodate industry standard application-specific integrated circuits (ASICs) interfaces, such as from a 12 bit ADC core to an 8 bit digital interface.
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