公开(公告)号：EP1388053A4

公开(公告)日：2008-04-16

申请号：EP01987447

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3885

Abstract: A method and apparatus for issuing and executing memory instructions so as to maximize the number of requests issued to a highly pipelined memory and avoid reading data from memory (10) before a corresponding write to memory (10). The memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.