SYSTEM FOR EMBEDDING ADDITIONAL INFORMATION IN VIDEO DATA, AND EMBEDDING METHOD
    1.
    发明公开
    SYSTEM FOR EMBEDDING ADDITIONAL INFORMATION IN VIDEO DATA, AND EMBEDDING METHOD 有权
    系统和方法嵌入视频附加信息

    公开(公告)号:EP1139660A9

    公开(公告)日:2002-03-20

    申请号:EP98955969

    申请日:1998-11-25

    Applicant: IBM

    Abstract: An intra-block of the I-frame or P,B-frame is detected from an MPEG stream. When it is detected, one macro block of data is taken out from the MPEG stream and buffered. The buffered macro block is embedded with a pattern so that the length of the VLC may be invariant. The macro block embedded with a pattern is returned back to the MPEG stream. More specifically, the DC component is detected from the buffered macro block and a pseudo-random number is generated in order to generate a pattern to be embedded. It is judged whether or not the bit length of the DC component is invariant when the generated pattern is embedded. If the bit length is invariant, the pattern is embedded in the buffered macro block. When the bit length is varied, it is judged whether or not half of the pattern can be embedded. If possible, the pattern is embedded.

    SYSTEM FOR EMBEDDING ADDITIONAL INFORMATION IN VIDEO DATA, AND EMBEDDING METHOD
    2.
    发明公开
    SYSTEM FOR EMBEDDING ADDITIONAL INFORMATION IN VIDEO DATA, AND EMBEDDING METHOD 有权
    系统和方法嵌入视频附加信息

    公开(公告)号:EP1139660A4

    公开(公告)日:2003-02-26

    申请号:EP98955969

    申请日:1998-11-25

    Applicant: IBM

    Abstract: An intra-block of the I-frame or P,B-frame is detected from an MPEG stream. When it is detected, one macro block of data is taken out from the MPEG stream and buffered. The buffered macro block is embedded with a pattern so that the length of the VLC may be invariant. The macro block embedded with a pattern is returned back to the MPEG stream. More specifically, the DC component is detected from the buffered macro block and a pseudo-random number is generated in order to generate a pattern to be embedded. It is judged whether or not the bit length of the DC component is invariant when the generated pattern is embedded. If the bit length is invariant, the pattern is embedded in the buffered macro block. When the bit length is varied, it is judged whether or not half of the pattern can be embedded. If possible, the pattern is embedded.

    DATA HIDING METHOD AND DATA EXTRACTING METHOD
    4.
    发明公开
    DATA HIDING METHOD AND DATA EXTRACTING METHOD 失效
    方法用于隐藏和提取数据

    公开(公告)号:EP0852441A4

    公开(公告)日:2003-01-15

    申请号:EP97902686

    申请日:1997-02-13

    Applicant: IBM

    Abstract: A data hiding method for hiding message data in media data and a data extracting method for extracting message data hidden in the media data. In the data hiding method, the message data are dispersedly hidden in the media data so that no third person can alter the message data. Specifically, the array elements of a message array are dispersedly hidden in a media array based on a status value S designating a specific array element in the media array when the media data and message data are expressed as the media array and the message array, respectively. The hiding method includes (a) a step of determining the j-th (j≥0) status value Sj, (b) a step of determining the (j+1)-th status value Sj+1 based on the value Sj, the array element of the media array designated by the value Sj and the above-mentioned array element of the message array, and (c) a step of hiding data to be hidden in the array element of the media array designated by the value Sj+1.

    SIMULATION METHOD, SYSTEM AND PROGRAM
    5.
    发明公开

    公开(公告)号:EP2608040A4

    公开(公告)日:2018-02-07

    申请号:EP11818040

    申请日:2011-07-27

    Applicant: IBM

    CPC classification number: G06F17/5009 G05B17/02 G06F11/261

    Abstract: Simulation of a system with a plurality of ECU is rapidly executed while avoiding deadlock by performing conservative event synchronization. A simulation system is provided with 4 layers, namely a processor emulator which is an ECU emulator, a plant simulator, and external peripheral scheduler, and a mutual peripheral scheduler. The external peripheral scheduler performs advanced execution of the plant simulator only during processor emulator reaction delay time (or the time until the next event). Furthermore, notification to perform advanced execution of the processor emulator is provided until the actual plant simulator stop time. The mutual peripheral scheduler provides notification to the processor emulator to perform advanced execution only during communication delay timing between processor emulators (or the time until the next event). The processor emulator conservatively processes until the earliest time of the notification times. Each peripheral proceeds with processing until the earliest time of the accepted events.

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