TRANSISTOR WITH LOW PARASITIC CAPACITANCE
    1.
    发明公开

    公开(公告)号:EP4199115A1

    公开(公告)日:2023-06-21

    申请号:EP21215532.9

    申请日:2021-12-17

    申请人: IMEC VZW

    摘要: According to an aspect of the present inventive concept there is provided a 2D transistor device (100). The 2D transistor device (100) comprises: a 2D semiconductor layer (110) comprising a source-side extension portion (112), a drain-side extension portion (116) and a channel portion (114) extending between the extension portions (112, 116) along a channel direction (300); a gate electrode (120) arranged along and being coextensive with the channel portion (114); a source-side 2D metal contact (132) arranged in abutment with the source-side extension portion (112) and spaced apart from the gate electrode (120) along the channel direction (300); and a drain-side 2D metal contact (136) arranged in abutment with the drain-side extension portion (116) and spaced apart from the gate electrode (120) along the channel direction (300).
    A method (150) for forming such a device (100) and a system (200) comprising at least two such devices (100) are also provided.