公开(公告)号：EP3340247B1

公开(公告)日：2020-02-26

申请号：EP17208290.1

申请日：2017-12-19

申请人： IMEC vzw ,  Vrije Universiteit Brussel ,  Katholieke Universiteit Leuven

发明人： Sakhare, Sushil ,  Huynh Bao, Trong ,  Perumkunnil, Manu Komalan

IPC分类号： G11C14/00 ,  G11C11/412 ,  G11C11/419 ,  G11C11/417 ,  G11C13/00 ,  G11C11/16

公开(公告)号：EP3340247A1

公开(公告)日：2018-06-27

申请号：EP17208290.1

申请日：2017-12-19

申请人： IMEC vzw ,  Vrije Universiteit Brussel ,  Katholieke Universiteit Leuven

发明人： Sakhare, Sushil ,  Huynh Bao, Trong ,  Perumkunnil, Manu Komalan

IPC分类号： G11C14/00 ,  G11C11/412 ,  G11C11/419 ,  G11C11/16

摘要： A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.