公开(公告)号：EP3969984A1

公开(公告)日：2022-03-23

申请号：EP20806293.5

申请日：2020-03-19

申请人： INTEL Corporation

发明人： ANANTHAKRISHNAN, Avinash N. ,  AMBARDEKAR, Ameya ,  VARMA, Ankush ,  ANGEL, Nimrod ,  ROSENZWEIG, Nir ,  GIHON, Arik ,  GENDLER, Alexander ,  RAYESS, Rachid E. ,  SALUS, Tamir

IPC分类号： G06F1/3234 ,  G06F1/3296

公开(公告)号：EP3923120A1

公开(公告)日：2021-12-15

申请号：EP20213342.7

申请日：2020-12-11

申请人： INTEL Corporation

发明人： GENDLER, Alexander ,  ANGEL, Nimrod ,  AMBARDEKAR, Ameya ,  WIJERATNE, Sapumal ,  SCHIFF, Tod ,  VIJ, Vikas ,  Uan-Zo-Li, Alexander

IPC分类号： G06F1/3212 ,  G06F1/324 ,  G06F1/3296

摘要： A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 µS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).