公开(公告)号：EP3757859A3

公开(公告)日：2021-01-13

申请号：EP20162644.7

申请日：2020-03-12

申请人： INTEL Corporation

发明人： ZMUDZINSKI, Krystof C. ,  JOHNSON, Simon P. ,  MAKARAM, Raghunandan ,  McKEEN, Francis X. ,  ROZAS, Carlos V. ,  OZSOY, Meltem ,  ALEXANDROVICH, Ilya ,  CHHABRA, Siddartha

IPC分类号： G06F21/79 ,  G06F12/14

摘要： A processor includes a cryptographic engine to control access, using an secure region key identifier (ID), to one or more memory range of memory allocable for flexible conversion to secure pages of architecturally-protected memory regions, and a processor core. The processor core is to, responsive to receipt of a request to access the memory, perform a walk of page tables and extended page tables to translate a linear address of the request to a physical address of the memory. The processor core is further to determine that the physical address corresponds to an secure page within the one or more memory range of the memory, that a first key ID located within the physical address does not match the secure region key ID, and issue a page fault and deny access to the secure page in the memory.