公开(公告)号：EP3588314A1

公开(公告)日：2020-01-01

申请号：EP19177146.8

申请日：2019-05-28

申请人： INTEL Corporation

发明人： LIU, Fangfei ,  XING, Bin ,  STEINER, Michael ,  VIJ, Mona ,  ROZAS, Carlos ,  MCKEEN, Francis ,  OZSOY, Meltem ,  FERNANDEZ, Matthew ,  ZMUDZINSKI, Krystof ,  SHANAHAN, Mark

IPC分类号： G06F12/14

摘要： Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.