公开(公告)号：EP3671834A1

公开(公告)日：2020-06-24

申请号：EP19209587.5

申请日：2019-11-15

申请人： Intel Corporation

发明人： JACK, Nathan ,  DOMANSKI, Krzysztof

IPC分类号： H01L27/02 ,  H01L29/06

摘要： A guard ring grid is disclosed. The guard ring grid includes a substrate and an injector array coupled to the substrate. The injector array includes a plurality of injectors. The guard ring grid also includes a plurality of guard rings that surround the plurality of injectors.

公开(公告)号：EP4109561A1

公开(公告)日：2022-12-28

申请号：EP22164224.2

申请日：2022-03-24

申请人： INTEL Corporation

发明人： ORR, Benjamin ,  KOLLURU, Kalyan ,  KAR, Ayan ,  OMAR, Sabih ,  GUHA, Biswajeet ,  THOMSON, Nicholas ,  MA, Rui ,  LIN, Chung-Hsun ,  GREENE, Brian ,  HU, Lin ,  JACK, Nathan

IPC分类号： H01L29/861 ,  H01L29/868 ,  H01L29/06 ,  H01L29/08 ,  H01L27/02 ,  H01L21/329 ,  H01L29/40 ,  H01L23/34

摘要： Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

公开(公告)号：EP4109546A1

公开(公告)日：2022-12-28

申请号：EP22169011.8

申请日：2022-04-20

申请人： INTEL Corporation

发明人： MA, Rui ,  KOLLURU, Kalyan ,  THOMSON, Nicholas ,  KAR, Ayan ,  ORR, Benjamin ,  JACK, Nathan ,  GUHA, Biswajeet ,  GREENE, Brian ,  LIN, Chung-Hsun

IPC分类号： H01L29/06 ,  H01L27/04 ,  H01L29/74 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/10

摘要： Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

公开(公告)号：EP4109531A1

公开(公告)日：2022-12-28

申请号：EP22164177.2

申请日：2022-03-24

申请人： Intel Corporation

发明人： GROVER, Rohit ,  ORR, Benjamin ,  KOLLURU, Kalyan ,  JACK, Nathan ,  THOMSON, Nicholas ,  KAR, Ayan ,  MA, Rui

IPC分类号： H01L27/02 ,  H01L21/8234

摘要： A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.

公开(公告)号：EP3840045A1

公开(公告)日：2021-06-23

申请号：EP20197775.8

申请日：2020-09-23

申请人： INTEL Corporation

发明人： GUHA, Biswajeet ,  HSU, William ,  LIN, Chung-Hsun ,  PHOA, Kinyip ,  GOLONZKA, Oleg ,  GHANI, Tahir ,  KOLLURU, Kalyan ,  JACK, Nathan ,  THOMSON, Nicholas ,  KAR, Ayan ,  ORR, Benjamin

IPC分类号： H01L27/088 ,  H01L29/06 ,  B82Y10/00 ,  H01L21/74 ,  H01L27/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L27/02 ,  H01L21/336

摘要： Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.