公开(公告)号：EP3731500A1

公开(公告)日：2020-10-28

申请号：EP20161586.1

申请日：2020-03-06

申请人： INTEL Corporation

发明人： MEDVEDKIN, Vladimir ,  CHILIKIN, Andrey

IPC分类号： H04L29/12

摘要： Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.