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1.发明公开
公开(公告)号：EP4290370A1
公开(公告)日：2023-12-13
申请号：EP23181292.6
申请日：2018-03-14
申请人： Intel Corporation
发明人： Ould-Ahmed-Vall, ElMoustapha , Lakshmanan, Barath , Shpeisman, Tatiana , Ray, Joydeep , Tang, Ping T. , Strickland, Michael , Chen, Xiaoming , Yao, Anbang , Ashbaugh, Ben J. , Hurd, Linda L. , Ma, Liwei
摘要： One embodiment provides for data processing system to perform machine learning operations. The data processing system comprises: a memory device configured to store instructions; a graphics processing unit (GPU) to execute the instructions. The instructions include a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, and the second instruction to cause the GPU to perform an integer operation. A general-purpose graphics compute unit included within the GPU has a single instruction, multiple thread architecture and is to execute the first instruction concurrently with execution of the second instruction.
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公开(公告)号：EP3955203A3
公开(公告)日：2022-03-09
申请号：EP21181091.6
申请日：2018-03-02
申请人： INTEL Corporation
发明人： Appu, Abhishek R. , Koker, Altug , Weast, John C. , MacPherson, Mike B. , Hurd, Linda L. , Baghsorkhi, Sara S. , Gottschlich, Justin E. , Surti, Prasoonkumar , Sakthivel, Chandrasekaran , Ma, Liwei , Ould-Ahmed-Vall, ElMoustapha , Sinha, Kamal , Ray, Joydeep , Vembu, Balaji , Jahagirdar, Sanjeev , Ranganathan, Vasanth , Kim, Dukhwan
IPC分类号： G06T1/20
摘要： A method of embodiments, as described herein, includes scheduling resources in a system for a plurality of contexts, the resources of the system including multiple streaming processors; specifying a portion of available threads as a limitation on usage of the multiple streaming processors; and upon determining that the limitation on usage of the multiple streaming processors is set, limiting usage of the multiple streaming processors by one or more contexts of the plurality of contexts. Limiting usage of the multiple streaming processors includes limiting threads for the one or more contexts to the specified portion of available threads of the multiple streaming processors, the specified portion being less than all available threads of the multiple streaming processors. Limiting threads for the one or more contexts to the specified portion of available threads includes limiting the one or more contexts to a subset of the multiple streaming processors, the subset being less than all available streaming processors.
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公开(公告)号：EP4099168A1
公开(公告)日：2022-12-07
申请号：EP22175421.1
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Ould-Ahmed-Vall, ElMoustapha , Baghsorkhi, Sara S. , Yao, Anbang , Nealis, Kevin , Chen, Xiaoming , Koker, Altug , Appu, Abhishek R. , Weast, John C. , MacPherson, Mike B. , Kim, Dukhwan , Hurd, Linda L. , Ashbaugh, Ben J. , Lakshmanan, Barath , Ma, Liwei , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S.
IPC分类号： G06F9/50 , G06T15/00 , G06F9/30 , G06F9/38 , G06N3/04 , G06N3/063 , G06N3/08 , G06T1/20 , G06F12/0811
摘要： Disclosed herein is a graphics processor comprising a memory device, a level-two (L2) cache memory and a raster operations unit (ROP) coupled with the memory device, a compressor to perform lossless compression on data to be written to the memory device, and a streaming multiprocessor coupled with the memory device. The streaming multiprocessor is to concurrently execute multiple thread groups. The streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The multiple instructions include a first instruction to cause at least a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands and a second instruction to cause at least a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands, the first instruction to execute concurrently with the second instruction. The streaming multiprocessor includes a mixed precision core to perform operations for at least a third instruction of the multiple instructions. The mixed precision core is to perform a first operation of the third instruction at a first precision and a second operation of the third instruction at a second precision. The first operation is a multiply having at least one 16-bit floating-point input, and the second operation is an accumulate having a 32-bit floating-point input.
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公开(公告)号：EP3955203A2
公开(公告)日：2022-02-16
申请号：EP21181091.6
申请日：2018-03-02
申请人： INTEL Corporation
发明人： Appu, Abhishek R. , Koker, Altug , Weast, John C. , MacPherson, Mike B. , Hurd, Linda L. , Baghsorkhi, Sara S. , Gottschlich, Justin E. , Surti, Prasoonkumar , Sakthivel, Chandrasekaran , Ma, Liwei , Ould-Ahmed-Vall, ElMoustapha , Sinha, Kamal , Ray, Joydeep , Vembu, Balaji , Jahagirdar, Sanjeev , Ranganathan, Vasanth , Kim, Dukhwan
IPC分类号： G06T1/20
摘要： A method of embodiments, as described herein, includes scheduling resources in a system for a plurality of contexts, the resources of the system including multiple streaming processors; specifying a portion of available threads as a limitation on usage of the multiple streaming processors; and upon determining that the limitation on usage of the multiple streaming processors is set, limiting usage of the multiple streaming processors by one or more contexts of the plurality of contexts. Limiting usage of the multiple streaming processors includes limiting threads for the one or more contexts to the specified portion of available threads of the multiple streaming processors, the specified portion being less than all available threads of the multiple streaming processors. Limiting threads for the one or more contexts to the specified portion of available threads includes limiting the one or more contexts to a subset of the multiple streaming processors, the subset being less than all available streaming processors.
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5.发明公开
公开(公告)号：EP3958116A1
公开(公告)日：2022-02-23
申请号：EP21202337.8
申请日：2018-03-14
申请人： INTEL Corporation
发明人： Ould-Ahmed-Vall, ElMoustapha , Lakshmanan, Barath , Shpeisman, Tatiana , Ray, Joydeep , Tang, Ping T. , Strickland, Michael , Chen, Xiaoming , Yao, Anbang , Ashbaugh, Ben J. , Hurd, Linda L. , Ma, Liwei
摘要： One embodiment provides for a compute apparatus to perform machine learning operations. The compute apparatus comprises: instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions; and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.
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公开(公告)号：EP4325424A3
公开(公告)日：2024-05-08
申请号：EP23220686.2
申请日：2018-03-02
申请人： INTEL Corporation
发明人： Appu, Abhishek R. , Koker, Altug , Weast, John C. , MacPherson, Mike B. , Hurd, Linda L. , Baghsorkhi, Sara S. , Gottschlich, Justin E. , Surti, Prasoonkumar , Sakthivel, Chandrasekaran , Ma, Liwei , Ould-Ahmed-Vall, ElMoustapha , Sinha, Kamal , Ray, Joydeep , Vembu, Balaji , Jahagirdar, Sanjeev , Ranganathan, Vasanth , Kim, Dukhwan
IPC分类号： G06T1/20
摘要： A method of embodiments, as described herein, includes scheduling resources in a system for a plurality of contexts, the resources of the system including multiple streaming processors; specifying a portion of available threads as a limitation on usage of the multiple streaming processors; and upon determining that the limitation on usage of the multiple streaming processors is set, limiting usage of the multiple streaming processors by one or more contexts of the plurality of contexts. Limiting usage of the multiple streaming processors includes limiting threads for the one or more contexts to the specified portion of available threads of the multiple streaming processors, the specified portion being less than all available threads of the multiple streaming processors. Limiting threads for the one or more contexts to the specified portion of available threads includes limiting the one or more contexts to a subset of the multiple streaming processors, the subset being less than all available streaming processors.
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公开(公告)号：EP4325424A2
公开(公告)日：2024-02-21
申请号：EP23220686.2
申请日：2018-03-02
申请人： INTEL Corporation
发明人： Appu, Abhishek R. , Koker, Altug , Weast, John C. , MacPherson, Mike B. , Hurd, Linda L. , Baghsorkhi, Sara S. , Gottschlich, Justin E. , Surti, Prasoonkumar , Sakthivel, Chandrasekaran , Ma, Liwei , Ould-Ahmed-Vall, ElMoustapha , Sinha, Kamal , Ray, Joydeep , Vembu, Balaji , Jahagirdar, Sanjeev , Ranganathan, Vasanth , Kim, Dukhwan
IPC分类号： G06T1/20
摘要： A method of embodiments, as described herein, includes scheduling resources in a system for a plurality of contexts, the resources of the system including multiple streaming processors; specifying a portion of available threads as a limitation on usage of the multiple streaming processors; and upon determining that the limitation on usage of the multiple streaming processors is set, limiting usage of the multiple streaming processors by one or more contexts of the plurality of contexts. Limiting usage of the multiple streaming processors includes limiting threads for the one or more contexts to the specified portion of available threads of the multiple streaming processors, the specified portion being less than all available threads of the multiple streaming processors. Limiting threads for the one or more contexts to the specified portion of available threads includes limiting the one or more contexts to a subset of the multiple streaming processors, the subset being less than all available streaming processors.
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