公开(公告)号：EP4202695A1

公开(公告)日：2023-06-28

申请号：EP22208765.2

申请日：2022-11-22

申请人： INTEL Corporation

发明人： Sha, Swaraj ,  Nori, Anant Vithal ,  Subramoney, Sreenivas ,  Shwartsman, Stanislav ,  Kryukov, Pavel I ,  Rappoport, Lihu

IPC分类号： G06F12/0862

摘要： An apparatus includes memory circuitry including a first data structure and prefetch circuitry that is coupled to the memory circuitry. The prefetch circuitry is to store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program. The first subregion entry is to include a plurality of delta values. A first delta value of the plurality of delta values represents a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region. The prefetch circuitry is further to detect a first memory access of a first cache line in the first subregion, identify prefetch candidates based on the first cache line and the plurality of delta values, and issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.

公开(公告)号：EP4020227A1

公开(公告)日：2022-06-29

申请号：EP21196229.5

申请日：2021-09-13

申请人： Intel Corporation

发明人： Kallurkar, Prathmesh ,  Nori, Anant Vithal ,  Subramoney, Sreenivas

IPC分类号： G06F12/084 ,  G06F12/0846 ,  G06F12/0895

摘要： An embodiment of an integrated circuit may comprise a core, a first level core cache memory coupled to the core, a shared core cache memory coupled to the core, a first cache controller coupled to the core and communicatively coupled to the first level core cache memory, a second cache controller coupled to the core and communicatively coupled to the shared core cache memory, and circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero. Other embodiments are disclosed and claimed.

公开(公告)号：EP4198749A1

公开(公告)日：2023-06-21

申请号：EP22206038.6

申请日：2022-11-08

申请人： Intel Corporation

发明人： Nori, Anant Vithal ,  Kallurkar, Prathmesh ,  Soundararajan, Niranjan Kumar ,  Subramoney, Sreenivas ,  Rappoport, Lihu ,  Alam, Hanna ,  Moga, Adrian ,  Singhal, Ronak

IPC分类号： G06F12/0897 ,  G06F9/30 ,  G06F12/126

摘要： Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3796180A1

公开(公告)日：2021-03-24

申请号：EP20179004.5

申请日：2020-06-09

申请人： INTEL Corporation

发明人： Bera, Rahul ,  Nori, Anant Vithal ,  Subramoney, Sreenivas

IPC分类号： G06F12/0862

摘要： Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page, generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature, perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature, receive a prefetch request for the single access signature, and perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.