公开(公告)号：EP3716079A1

公开(公告)日：2020-09-30

申请号：EP20154463.2

申请日：2020-01-30

申请人： INTEL Corporation

发明人： Rodgers, Scott Dion ,  Chappell, Chappell S. ,  Huntley, Barry E.

IPC分类号： G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14

摘要： An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register (1310) to store a first base address associated with program code executed at a first privilege level; a second control register (1320) to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table (1351) using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table (1361) using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.