公开(公告)号：EP3767462A1

公开(公告)日：2021-01-20

申请号：EP20163796.4

申请日：2020-03-18

申请人： INTEL Corporation

发明人： Chauhan, Adarsh ,  Sala, Franck ,  Gaur, Jayesh ,  Sperber, Zeev ,  Rappoport, Lihu ,  Yoaz, Adi ,  Subramoney, Sreenivas

IPC分类号： G06F9/38

摘要： Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.

公开(公告)号：EP4202661A1

公开(公告)日：2023-06-28

申请号：EP22203532.1

申请日：2022-10-25

申请人： Intel Corporation

发明人： Bandishte, Sumeet ,  Gaur, Jayesh ,  Sala, Franck ,  Sivtsov, Alexey Yurievich ,  Stark, Jared Warner, IV ,  Rappoport, Lihu ,  Subramoney, Sreenivas

IPC分类号： G06F9/38

摘要： Techniques and mechanisms for a processor to determine an execution of instructions based on a prediction of a taken branch. In an embodiment, a first prediction unit generates each of multiple branch predictions in one cycle of successive branch prediction cycles. An indication of the branch predictions is provided to an execution pipeline, which prepares to execute an instruction based on the indication. Where a first one of the branch predictions is determined to be of a low confidence type, said first branch prediction is further indicated to a second prediction unit, which performs a second branch prediction based on the same branch instruction for which the first branch prediction was made. In another embodiment, the second prediction unit signals that a state of the execution pipeline is to be cleared, based on a determination that the first and second branch predictions are inconsistent with each other.

公开(公告)号：EP4075280A1

公开(公告)日：2022-10-19

申请号：EP22174476.6

申请日：2020-05-20

申请人： Intel Corporation

发明人： Chauhan, Adarsh ,  Gaur, Jayesh ,  Sala, Franck ,  Rappoport, Lihu ,  Sperber, Zeev ,  Yoaz, Adi ,  Subramoney, Sreenivas

IPC分类号： G06F11/34 ,  G06F12/0862

摘要： Disclosed is a processor with a first cache, a second cache coupled to the first cache, an arithmetic logic unit (ALU) to perform arithmetic operations, and a circuit coupled to the ALU. After the processor has executed a workload for a first execution window with a microarchitectural feature disabled and for a second execution window with the microarchitectural feature enabled, the circuit is to: determine whether the processor achieved worse performance in the second execution window, relative to the first execution window; and in response to a determination that the processor achieved the worse performance in the second execution window, update a state for an address associated with an instruction towards a bad final state, wherein when the state for the address reaches the bad final state, the processor is to disable the microarchitectural feature for the address associated with the instruction. Other embodiments are described and claimed.

公开(公告)号：EP3796177A1

公开(公告)日：2021-03-24

申请号：EP20175698.8

申请日：2020-05-20

申请人： Intel Corporation

发明人： Chauhan, Adarsh ,  Gaur, Jayesh ,  Sala, Franck ,  Rappoport, Lihu ,  Sperber, Zeev ,  Yoaz, Adi ,  Subramoney, Sreenivas

IPC分类号： G06F11/34 ,  G06F12/0862

摘要： A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.