公开(公告)号：EP4202652A1

公开(公告)日：2023-06-28

申请号：EP22205225.0

申请日：2022-11-03

申请人： INTEL Corporation

发明人： Shwartsman, Stanislav ,  Shtiegmann, Elad ,  Bandishte, Sumeet ,  Rappoport, Lihu ,  Sperber, Zeev ,  Gaur, Jayesh

IPC分类号： G06F9/30 ,  G06F9/38

摘要： Techniques and mechanisms for efficiently making value prediction information available for use by in a processor. In an embodiment, the instruction execution is to include a loading of some data to a first location (e.g., a first register). A decoder of the processor accesses reference information which indicates that the execution is to comprise multiple micro-operations (µops) including a LoadCheck µop and a Move µop. The LoadCheck µop loads a first value to the first location, and checks whether the loaded first value is the same as a previously-determined second value which represents a prediction of what the first value would be. The Move µop moves the second value to the first location. In another embodiment, the Move µop is scheduled for execution out-of-order with respect to the LoadCheck µοp, resulting in an early availability of the second value for access in a register file by another µop.