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公开(公告)号：EP1466454B1
公开(公告)日：2008-12-03
申请号：EP02755370.0
申请日：2002-09-13
申请人： IPWireless, Inc.
IPC分类号： H04L27/00
CPC分类号： H04L27/0014 , H04L2027/0028 , H04L2027/0065
摘要： A method and arrangement for automatic frequency correction in UTRA TDD mode, having a first stage (500) for frequency lock in idle mode, and a second stage (600) for receiving a channel estimate from beacon function (mx1), receiving a channel estimate from at least one other physical channel (mx2), and receiving output from a primary synchronisation code correlator (mx0,pc1,pc2), and for producing therefrom signals (X,Y,N) for use in frequency correction. By utilising first and second partial correlation values (pc1,pc2) which are balanced, DC offset effects may be substantially removed. This provides the following advantage of significantly improving performance at low levels of SNR, and removal of DC offset effects provides immunity to DC offsets arising from imperfections in hardware.
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公开(公告)号：EP1466454A1
公开(公告)日：2004-10-13
申请号：EP02755370.0
申请日：2002-09-13
申请人： IPWireless, Inc.
IPC分类号： H04L27/00
CPC分类号： H04L27/0014 , H04L2027/0028 , H04L2027/0065
摘要： A method and arrangement for automatic frequency correction in UTRA TDD mode, having a first stage (500) for frequency lock in idle mode, and a second stage (600) for receiving a channel estimate from beacon function (mx1), receiving a channel estimate from at least one other physical channel (mx2), and receiving output from a primary synchronisation code correlator (mx0,pc1,pc2), and for producing therefrom signals (X,Y,N) for use in frequency correction. By utilising first and second partial correlation values (pc1,pc2) which are balanced, DC offset effects may be substantially removed. This provides the following advantage of significantly improving performance at low levels of SNR, and removal of DC offset effects provides immunity to DC offsets arising from imperfections in hardware.
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