摘要:
A spread-spectrum demodulator architecture (10) is presented which utilizes parallel (Fig. 1) processing to accomplish rapid signal acquisition with simultaneous tracking of multiple channels, while implementing an integrated multi-element adaptive beamformer, Rake combiner, and multi-user detector (MUD). A matched filter computational architecture is utilized, in which common digital arithmetic elements are used for both acquisition and tracking purposes. As each channel is sequentially acquired by the parallel matched filter, a subset of the arithmetic elements are then dedicated to the subsequent tracking of that channel. Additionally, multiple data inputs and delay lines are present, connecting the sampled baseband data streams of numerous RF bands and antenna elements with the arithmetic elements. The matched filter/despreader processing is virtually independent of channel origin or utilization; e.g., CDMA users, RF bands, beamformer elements, or Rake Fingers. Integration of the beamformer weighting computation with the demodulator results in substantial savings by sharing the existing circuitry performing carrier tracking and AGC. An optimal demodulator solution can be achieved through unified 'space/time' processing, by providing all observables (element snapshots, Rake Fingers, carrier/symbol SNR/phase, etc.), for multiple channels, to a single adaptive algorithm processor that can beamform, Rake, and perform joint detection (MUD).
摘要:
A parallel digital matched filter is constructed which performs numerous simultaneous correlations of a received spread spectrum signal against various replica offsets of its spreading sequence. This allows for the rapid acquisition (12) of the received signal code phase, and subsequent handoff to tracking (14) for a multi-channel receiver. A novel matched filter computational architecture is utilized, in which common digital arithmetic elements are used for both acquisition and tracking purposes. As each channel is sequentially acquired by the parallel matched filter, a subset of the arithmetic elements are then dedicated to the subsequent tracking of that channel. This process is repeated, with the remaining available arithmetic elements accelerating the acquisition of the next channel, and so on, until all resources are allocated as tracking channels. Additionally, multiple data inputs and delay lines (10) are present in this architecture, and are available for processing at each arithmetic element. In this way, multiple signal bands and user channels may be integrated within a common receiver framework.