公开(公告)号：EP4343562A1

公开(公告)日：2024-03-27

申请号：EP23183037.3

申请日：2023-07-03

申请人： Intel Corporation

发明人： BAILUR, Nirmala ,  CHAUHAN, Shailendra Singh ,  A/L SASIDARAN, Dhinesh ,  CHEE, Pik Shen ,  GOPALAKRISHNAN, Venkataramani ,  GUNNAM, Mahesh ,  HUANG, Yi Jen ,  JANGILI GANGA, Siva Prasad ,  KALISWAMY, Karthi ,  KONG, Jackson Chung Peng ,  KOTAKONDA, Venkataramana ,  LIM, Kie Woon ,  MEDEPALLI, Uma ,  RAVALI, Pampala ,  SATHEESAKURUP, Sreejith ,  SUNDER RAMAN, Charuhasini ,  SAVARIEGO, Tomer ,  SHAH, Kunal ,  TAN, Chuen Ming ,  VANKUNAVATH, Ramesh ,  ZAMANI, M. Reza ,  BANU, W. Naznin ,  JEEVARATHINAM, Surendar ,  KODALI, Sindhusha ,  MAHAJAN, Rohit ,  SHARMA, Deepak ,  SHETTY, Madhura ,  VENKATARAUYAPPA, Manjunatha

IPC分类号： G06F13/38

摘要： Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.

公开(公告)号：EP4227768A1

公开(公告)日：2023-08-16

申请号：EP22199770.3

申请日：2022-10-05

申请人： INTEL Corporation

发明人： AP, Santhosh ,  CHANDRABOSE, Arunthathi ,  CHAUHAN, Shailendra Singh ,  HEGDE, Mythili

IPC分类号： G06F1/26

摘要： Embodiments herein relate to an electronic device that includes a system-on-chip (SoC). The electronic device may further include a USB port to provide a first identification signal that is at a first voltage and that is related to a charging process between a USB device to which the USB port is coupled an the electronic device. The electronic device may further include a power delivery (PD) controller to: generate, based on the first identification signal, a second identification signal at a second voltage that is lower than the first voltage; and provide the second identification signal to the SoC. Other embodiments may be described and claimed.