公开(公告)号：EP4155915A1

公开(公告)日：2023-03-29

申请号：EP22188907.4

申请日：2022-08-05

申请人： Intel Corporation

发明人： Ramakrishnan, Sundararajan ,  Combs, Jonathan ,  Licht, Martin J. ,  Srinath, Santhosh

IPC分类号： G06F9/38

摘要： Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.

公开(公告)号：EP4202659A1

公开(公告)日：2023-06-28

申请号：EP22210978.7

申请日：2022-12-02

申请人： Intel Corporation

发明人： Valentine, Robert ,  Wong, Wing Shek ,  Combs, Jonathan ,  Charney, Mark

IPC分类号： G06F9/30

摘要： Techniques for data type conversion are described. An example uses an instruction that is to include fields for an opcode, an identification of source operand location, and an identification of destination operand location, wherein the opcode is to indicate instruction processing circuitry is to convert a 16-bit floating-point value from the identified source operand location into a 32-bit floating point value and store that 32-bit floating point value in one or more data element positions of the identified destination operand.

公开(公告)号：EP4202660A1

公开(公告)日：2023-06-28

申请号：EP22210981.1

申请日：2022-12-02

申请人： Intel Corporation

发明人： Valentine, Robert ,  Wong, Wing Shek ,  Combs, Jonathan ,  Charney, Mark

IPC分类号： G06F9/30

摘要： Techniques for data type conversion via instruction are described. An exemplary instruction is to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：EP4202653A1

公开(公告)日：2023-06-28

申请号：EP22205710.1

申请日：2022-11-07

申请人： Intel Corporation

发明人： Valentine, Robert ,  Wong, Wing Shek ,  Combs, Jonathan ,  Charney, Mark

IPC分类号： G06F9/30

摘要： Techniques for data type conversion using an instruction are described. An exemplary instruction includes fields for an opcode, an identification of source operands, and an identification of destination operand, wherein the opcode is to indicate execution circuitry and/or memory access circuitry is to convert 32-bit floating point values from the identified source operands into 16-bit floating point values and store 16-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：EP4195037A1

公开(公告)日：2023-06-14

申请号：EP22206823.1

申请日：2022-11-11

申请人： INTEL Corporation

发明人： Licht, Martin ,  Combs, Jonathan

IPC分类号： G06F9/38 ,  G06F1/32

摘要： An embodiment of an integrated circuit may comprise a core and an instruction decoder communicatively coupled to the core to decode one or more instructions for execution by the core, where the instruction decoder includes two or more decode clusters in a parallel arrangement, and circuitry to offline a decode cluster of the two or more decode clusters. Other embodiments are disclosed and claimed.