公开(公告)号：EP1647119B1

公开(公告)日：2012-06-13

申请号：EP04777713.1

申请日：2004-07-08

申请人： Intel Corporation

发明人： GRIFFIN, Jed c/o Intel Corporation ,  JEX, Jerry ,  FORESTIER, Arnaud ,  VAKIL, Kersi ,  KOLLA, Abhimanyu

IPC分类号： H04L27/24 ,  H04L25/49 ,  H04L1/06 ,  H04L7/00

CPC分类号： H04L27/24 ,  H04L1/06 ,  H04L25/4904

摘要： In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.