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公开(公告)号:EP4028883A1
公开(公告)日:2022-07-20
申请号:EP20863993.0
申请日:2020-09-11
申请人: Intel Corporation
发明人: MCDONNELL, Niall , EADS, Gage , GANGULI, Mrittika , HIREMATH, Chetan , MANGAN, John , PALERMO, Stephen , RICHARDSON, Bruce , VERPLANKE, Edwin , MOSUR, Praveen , CHADDICK, Bradley , KHADE, Abhishek , LAYEK, Abhirupa , MAINI, Sarita , SHAH, Rahul , SHAH, Shrikant , BURROUGHS, William , SONNIER, David
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公开(公告)号:EP4020209A1
公开(公告)日:2022-06-29
申请号:EP21217626.7
申请日:2021-12-23
申请人: Intel Corporation
发明人: WANG, Ren , GOBRIEL, Sameh , PAUL, Somnath , WANG, Yipeng , AUTEE, Priya , LAYEK, Abhirupa , NARAYANA, Shaman , VERPLANKE, Edwin , GANGULI, Mrittika , TSAI, Jr-Shian , SOROKIN, Anton , BANERJEE, Suvadeep , DAVARE, Abhijit , KIRKPATRICK, Desmond , SANKARAN, Rajesh M. , TIMBADIYA Jaykant B. , KABISTHALAM MUTHUKUMAR, Sriram , RANGANATHAN, Narayan
摘要: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.
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