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    WAKE-UP AND SCHEDULING OF FUNCTIONS WITH CONTEXT HINTS
    1.
    发明公开
    WAKE-UP AND SCHEDULING OF FUNCTIONS WITH CONTEXT HINTS 审中-公开

    公开(公告)号：EP3770759A1

    公开(公告)日：2021-01-27

    申请号：EP20164722.9

    申请日：2020-03-20

    申请人： Intel Corporation

    发明人： BACHMUTSKY, Alexander ,  DOSHI, Kshitij ,  KONDAPALLI, Raghu ,  SUKHOMLINOV, Vadim

    IPC分类号： G06F9/48

    摘要： Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information.

    MEMORY WRITE LOG STORAGE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    2.
    发明公开
    MEMORY WRITE LOG STORAGE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开

    公开(公告)号：EP3525088A1

    公开(公告)日：2019-08-14

    申请号：EP19151260.7

    申请日：2019-01-10

    申请人： Intel Corporation

    发明人： DOSHI, Kshitij ,  DEMENTIEV, Roman ,  SUKHOMLINOV, Vadim

    IPC分类号： G06F9/30 ,  G06F9/38

    摘要： A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.

    TECHNOLOGIES FOR FILTERING NETWORK TRAFFIC ON INGRESS
    7.
    发明公开
    TECHNOLOGIES FOR FILTERING NETWORK TRAFFIC ON INGRESS 审中-公开

    公开(公告)号：EP3624416A1

    公开(公告)日：2020-03-18

    申请号：EP19191514.9

    申请日：2019-08-13

    申请人： INTEL Corporation

    发明人： CHILIKIN, Andrey ,  HYATT, Ronen Aharon ,  SUKHOMLINOV, Vadim

    IPC分类号： H04L29/06 ,  H04L12/851 ,  H04L12/741 ,  H04L12/721

    摘要： Technologies for filtering network traffic on ingress include a network interface controller (NIC) configured to parse a header of a network packet received by the NIC to extract data from a plurality of header fields of the header. The NIC is additionally configured to determine an input set based on the field vector, retrieve a matching list from a plurality of matching lists, and compare the input set to each of the plurality of rules to identify a matching rule of the plurality of rules that matches a corresponding portion of the input set. The NIC is further configured to perform an action on the network packet based on an actionable instruction associated with the one of the plurality of rules that matches the corresponding portion of the input set. Other embodiments are described herein.