公开(公告)号：EP3991008A1

公开(公告)日：2022-05-04

申请号：EP20831817.0

申请日：2020-03-19

申请人： Intel Corporation

发明人： VANGAL, Sriram R. ,  MALLANAYAKANAHALLI DEVARAJU, Jayanth ,  DE, Vivek ,  MILSTREY, Robert ,  GUNTHER, Stephen H.

IPC分类号： G06F1/32 ,  G06F11/30

公开(公告)号：EP2553893A2

公开(公告)日：2013-02-06

申请号：EP11766442.5

申请日：2011-03-29

申请人： Intel Corporation

发明人： VANGAL, Sriram R. ,  BORKAR, Nitin Y. ,  FANG, Zhen

IPC分类号： H04L29/02 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L47/30 ,  H04L47/39 ,  H04L49/109 ,  H04L49/40

摘要： In one embodiment, a method includes comparing an occupancy level of a buffer of a port of a router to a threshold, and controlling the port to operate at a first voltage and frequency based at least in part on the comparison, and at least one other port of the router is controlled to operate at a second voltage and frequency. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，一种方法包括：将路由器的端口的缓冲器的占用水平与阈值进行比较，并且至少部分地基于该比较来控制端口以第一电压和频率进行操作;以及至少一个其他 控制路由器的端口以第二电压和频率工作。 描述并要求保护其他实施例。

公开(公告)号：EP4152014A1

公开(公告)日：2023-03-22

申请号：EP22181831.3

申请日：2022-06-29

申请人： INTEL Corporation

发明人： KHELLAH, Muhammad ,  TSCHANZ, James ,  KOEBERL, Patrick ,  TOKUNAGA, Carlos ,  VANGAL, Sriram R. ,  PATEL, Pratik ,  BANG, Suyoung ,  BAUTISTA GABRIEL, Miguel Mario

IPC分类号： G01R19/165 ,  G06F21/75 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/17768 ,  H03K19/1778 ,  H03K19/17784

摘要： A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：EP2553893B1

公开(公告)日：2014-10-08

申请号：EP11766442.5

申请日：2011-03-29

申请人： Intel Corporation

发明人： VANGAL, Sriram R. ,  BORKAR, Nitin Y. ,  FANG, Zhen

IPC分类号： H04L12/70

CPC分类号： H04L47/30 ,  H04L47/39 ,  H04L49/109 ,  H04L49/40