公开(公告)号：EP1323131B1

公开(公告)日：2007-02-28

申请号：EP01973598.4

申请日：2001-09-26

申请人： INTEL CORPORATION

发明人： TSAI, Hsin-Chu ,  MAIYURAN, Subramania ,  WANG, Chung-Chi

IPC分类号： G06T1/20

CPC分类号： G06T15/005

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.

公开(公告)号：EP2519892A2

公开(公告)日：2012-11-07

申请号：EP10841477.2

申请日：2010-12-10

申请人： Intel Corporation

发明人： NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J. ,  WANG, Chung-Chi

IPC分类号： G06F15/177

CPC分类号： G06F15/7871

摘要： In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached system reconfiguration code and data in order to dynamically reconfigure the hardware. Other embodiments are described and claimed.

公开(公告)号：EP1323131A2

公开(公告)日：2003-07-02

申请号：EP01973598.4

申请日：2001-09-26

申请人： INTEL CORPORATION

发明人： TSAI, Hsin-Chu ,  MAIYURAN, Subramania ,  WANG, Chung-Chi

IPC分类号： G06T1/00

CPC分类号： G06T15/005

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.