公开(公告)号：EP4104087A1

公开(公告)日：2022-12-21

申请号：EP20918345.8

申请日：2020-12-26

申请人： Intel Corporation

发明人： DURHAM, David M. ,  LEMAY, Michael D. ,  SULTANA, Salmin ,  GREWAL, Karanvir S. ,  KOUNAVIS, Michael E. ,  DEUTSCH, Sergej ,  WEILER, Andrew James ,  BASAK, Abhishek ,  BAUM, Dan ,  GHOSH, Santosh

IPC分类号： G06F21/78 ,  G06F21/72 ,  G06F12/14 ,  H04L9/06 ,  H04L9/08

公开(公告)号：EP4020272A1

公开(公告)日：2022-06-29

申请号：EP21196104.0

申请日：2021-09-10

申请人： INTEL Corporation

发明人： DURHAM, David M. ,  GREWAL, Karanvir S. ,  LEMAY, Michael D. ,  WEILER, Andrew James ,  SULTANA, Salim

IPC分类号： G06F21/52 ,  G06F21/72 ,  G06F12/14 ,  G06F9/35 ,  H04L9/08 ,  H04L9/06

摘要： A processor includes a register to store an encoded pointer to a variable in stack memory. The encoded pointer includes an encrypted portion and a fixed plaintext portion of a memory address corresponding to the variable. The processor further includes circuitry to, in response to a memory access request for associated with the variable, decrypt the encrypted portion of the encoded pointer to obtain first upper address bits of the memory address and a memory allocation size for a variable, decode the encoded pointer to obtain the memory address, verify the memory address is valid based, at least in part on the memory allocation size, and in response to determining that the memory address is valid, allow the memory access request.