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公开(公告)号：EP0055803A3
公开(公告)日：1983-11-09
申请号：EP81108551
申请日：1981-10-20
CPC分类号： G11C16/0433
摘要： A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1-T3) includes an enhanced conduction insulator (24) and means (T1, T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).
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公开(公告)号：EP0083418A2
公开(公告)日：1983-07-13
申请号：EP82111116.8
申请日：1982-12-02
IPC分类号： G11C11/00
CPC分类号： G11C14/00
摘要： This invention provides improved non-volatile semiconductor memories which form non-inverting signals and which include a one device dynamic volatile memory circuit having a storage capacitor (C,) which includes a conductive plate (12), a charged floating gate (FG) and an inversion layer (10) in a semiconductor substrate (18) together with a non-volatile device including the floating gate (FG), a control electrode (24) and a voltage divider having first and second serially-connected capacitors (C2, C1), with the floating gate (FG) being disposed at the common point between the first and second capacitors (C2, C1). The plate (12) of the storage capacitor (C,) is connected to a reference voltage source. The control electrode (24) is capacitively coupled to the floating gate (FG) through the first capacitor (C2) which includes a charge or electron injector structure. The capacitance of the first capacitor (C2) has a value, preferably, substantially less than that of the second capacitor (C1) which is formed between the floating gate (FG) and the semiconductor substrate (18).
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公开(公告)号：EP0083699A3
公开(公告)日：1984-09-26
申请号：EP82109890
申请日：1982-10-26
IPC分类号： H01L27/02
CPC分类号： H01L27/0288 , H01L27/0255
摘要： An input pad overvoltage protective circuit for integrated devices is disclosed. It enables both positive and negative polarity input signals be applied to a protected gate (14) of an FET (11). The protective circuit comprises a first resistor (12) coupled between an input pad (131 and the gate (14) and a current limiting second resistor (15) and diode (16) coupled between the pad and a reference potential.
摘要翻译： 公开了一种用于集成器件的输入焊盘过电压保护电路。 它使得正极性和负极性输入信号能够施加到FET（11）的受保护的栅极（14）。 保护电路包括耦合在输入焊盘（13）和栅极（14）之间的第一电阻器（12）和耦合在焊盘和参考电位之间的限流第二电阻器（15）和二极管（16）。
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公开(公告)号：EP0083699A2
公开(公告)日：1983-07-20
申请号：EP82109890.2
申请日：1982-10-26
IPC分类号： H01L27/02
CPC分类号： H01L27/0288 , H01L27/0255
摘要： An input pad overvoltage protective circuit for integrated devices is disclosed. It enables both positive and negative polarity input signals be applied to a protected gate (14) of an FET (11). The protective circuit comprises a first resistor (12) coupled between an input pad (131 and the gate (14) and a current limiting second resistor (15) and diode (16) coupled between the pad and a reference potential.
摘要翻译： 公开了一种用于集成器件的输入焊盘过电压保护电路。 它使得正极性和负极性输入信号能够施加到FET（11）的受保护的栅极（14）。 保护电路包括耦合在输入焊盘（13）和栅极（14）之间的第一电阻器（12）和耦合在焊盘和参考电位之间的限流第二电阻器（15）和二极管（16）。
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公开(公告)号：EP0083418A3
公开(公告)日：1986-04-16
申请号：EP82111116
申请日：1982-12-02
IPC分类号： G11C11/00
CPC分类号： G11C14/00
摘要： This invention provides improved non-volatile semiconductor memories which form non-inverting signals and which include a one device dynamic volatile memory circuit having a storage capacitor (C,) which includes a conductive plate (12), a charged floating gate (FG) and an inversion layer (10) in a semiconductor substrate (18) together with a non-volatile device including the floating gate (FG), a control electrode (24) and a voltage divider having first and second serially-connected capacitors (C2, C1), with the floating gate (FG) being disposed at the common point between the first and second capacitors (C2, C1). The plate (12) of the storage capacitor (C,) is connected to a reference voltage source. The control electrode (24) is capacitively coupled to the floating gate (FG) through the first capacitor (C2) which includes a charge or electron injector structure. The capacitance of the first capacitor (C2) has a value, preferably, substantially less than that of the second capacitor (C1) which is formed between the floating gate (FG) and the semiconductor substrate (18).
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公开(公告)号：EP0055803A2
公开(公告)日：1982-07-14
申请号：EP81108551.3
申请日：1981-10-20
CPC分类号： G11C16/0433
摘要： A memory system, particularly an electrically alterable read only memory system which includes a semiconductor substrate (10) having a diffusion region (12) therein defining one end of a channel region (14), a control plate (22, T1), a floating plate (20) separated from the channel region by a thin dielectric layer (16) and disposed between the control plate (22) and the channel region (14) and means (T1-T3) for transferring charge to and from the floating plate (22). A control gate (32) is coupled to the channel region (14) and is located between the diffusion region (12) and the floating plate (22). The control gate (32) may be connected to a word line and the diffusion region (12) may be connected to a bit/sense line. The channel region (14) is controlled by the word line and the presence or absence of charge on the floating plate (20). Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate (20). The charge transfer means (T1-T3) includes an enhanced conduction insulator (24) and means (T1, T3) for applying appropriate voltages to the control plate (22) and to the control gate (32) to transfer charge to and from the floating plate (20) through the enhanced conduction insulator (24).
摘要翻译： 一种存储器系统，特别是一种电可更改的只读存储器系统，其包括其中限定通道区域（14）的一端的扩散区（12）的半导体衬底（10），控制板（22，T1），浮置 平板（20）通过薄介电层（16）与沟道区分离并且设置在控制板（22）和沟道区域（14）之间，并且用于将电荷转移到浮动板（...） 22）。 控制栅极（32）耦合到沟道区域（14）并且位于扩散区域（12）和浮动板（22）之间。 控制栅极（32）可以连接到字线，并且扩散区域（12）可以连接到位/感测线。 通道区域（14）由字线控制，浮板（20）上是否存在电荷。 因此，可以通过检测在浮板（20）下存储在反相电容器中的电荷的存在或不存在来从存储器的单元读取信息。 电荷转移装置（T1，T3）包括增强的导电绝缘体（24）和用于向控制板（22）和控制栅极（32）施加适当电压的装置（T1-T3），以将电荷转移到 浮动板（20）通过增强的导电绝缘体（24）。
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