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公开(公告)号：EP0543512A3
公开(公告)日：1995-02-01
申请号：EP92309804.0
申请日：1992-10-27
发明人： Coleman, John Joseph , Coleman, Ronald Gerald , Monroe, Owen Keith , Stucke, Robert Frederick , Vanderbeck, Elizabeth Anne , Bello, Stephen Edward , Hattersley, John Robert , Hua, Kien Anh , Pruett, David Raymond , Rollo, Gerald Franklin
IPC分类号： G06F15/16
CPC分类号： G06F15/17375
摘要： A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processor is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviours in the protocol when message packets depart or when they arrive.
摘要翻译： 公开了一种并行计算机系统，包括使用交叉点或交叉开关连接在一起的多个高级处理器。 该系统在每个处理器和交换机之间包含一个适配器。 通过适配器执行协议处理以驱动交换机，传输页面和调度处理器之间的传输。 该协议使用类型化或标记缓冲区管理的概念，允许客户端绑定正在发送或接收的消息的语义。 这些语义在消息分组离开或到达时指定协议中的行为。
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公开(公告)号：EP0543512A2
公开(公告)日：1993-05-26
申请号：EP92309804.0
申请日：1992-10-27
发明人： Coleman, John Joseph , Coleman, Ronald Gerald , Monroe, Owen Keith , Stucke, Robert Frederick , Vanderbeck, Elizabeth Anne , Bello, Stephen Edward , Hattersley, John Robert , Hua, Kien Anh , Pruett, David Raymond , Rollo, Gerald Franklin
IPC分类号： G06F15/16
CPC分类号： G06F15/17375
摘要： A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processor is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviours in the protocol when message packets depart or when they arrive.
摘要翻译： 公开了一种并行计算机系统，其包括使用交叉点或横杆开关连接在一起的多个高级处理器。 该系统包括每个处理器和交换机之间的适配器。 用于驱动交换机的协议处理，在处理器之间传送页面和调度传输由适配器执行。 该协议使用类型化或标记的缓冲区管理的概念，允许客户端绑定正在发送或接收的消息的语义。 这些语义在消息包离开或到达时指定协议中的行为。
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公开(公告)号：EP0481248A2
公开(公告)日：1992-04-22
申请号：EP91116181.8
申请日：1991-09-24
IPC分类号： G06F15/40 , G06F15/419
CPC分类号： G06F15/8053 , G06F7/24 , G06F7/36 , G06F2207/222 , Y10S707/99937
摘要： A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provides input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered. By storing sorted keys (codewords) plus the address ID, reuse of codewords (in formation of longer strings, etc.) is made possible.
摘要翻译： 具有硬件逻辑节点寄存器和输出选择器加比较器的树分类器使得矢量处理器能够进行排序和合并操作。 每个周期提供一个输出记录的系统和方法提供了超过类似标量运算的性能提升。 由于在向量处理器中实现了硬件树和更新逻辑，因此存储流量的存储大大减少。 向量寄存器向硬件树结构提供输入数据。 按键和地址ID排序的输出记录放在存储器中。 多向量计数和多个向量中断索引（VIX）操作，字符串长度和合并掩码与向量合并指令结合使用。 数据输入记录键字段具有长格式和短格式。 可以使用实际的密钥数据或码字。 当遇到比较等号码字时，向量合并形成新的码字。 通过存储排序的密钥（码字）加上地址ID，可以重用码字（形成较长的字符串等）。
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公开(公告)号：EP0543512B1
公开(公告)日：1999-10-06
申请号：EP92309804.0
申请日：1992-10-27
发明人： Coleman, John Joseph , Coleman, Ronald Gerald , Monroe, Owen Keith , Stucke, Robert Frederick , Vanderbeck, Elizabeth Anne , Bello, Stephen Edward , Hattersley, John Robert , Hua, Kien Anh , Pruett, David Raymond , Rollo, Gerald Franklin
IPC分类号： G06F15/16
CPC分类号： G06F15/17375
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公开(公告)号：EP0481248A3
公开(公告)日：1993-07-28
申请号：EP91116181.8
申请日：1991-09-24
IPC分类号： G06F15/40 , G06F15/419
CPC分类号： G06F15/8053 , G06F7/24 , G06F7/36 , G06F2207/222 , Y10S707/99937
摘要： A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provides input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered. By storing sorted keys (codewords) plus the address ID, reuse of codewords (in formation of longer strings, etc.) is made possible.
摘要翻译： 具有硬件逻辑节点寄存器和输出选择器以及比较器的树分类器使得矢量处理器能够执行分类和合并操作。 每个周期提供一个输出记录的系统和方法相对于类似的标量操作提供了性能增强。 由于在矢量处理器中实现了硬件树和更新逻辑，因此存储到存储的流量急剧减少。 向量寄存器为硬件树结构提供输入数据。 按键排序的输出记录与地址ID一起放入存储区。 多向量计数和多向量中断索引（VIX）操作，字符串长度和合并掩码与矢量合并指令一起使用。 数据输入记录关键字段具有长格式和短格式。 可以使用实际的密钥数据或码字。 当比较相等的码字时，向量合并形成新的码字。 通过存储排序的密钥（码字）加上地址ID，可以重新使用码字（形成更长的字符串等）。
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