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公开(公告)号：EP0260459A2
公开(公告)日：1988-03-23
申请号：EP87111960.8
申请日：1987-08-18
发明人： Freeman, William Andrew , Wilson, Jacqueline Hegedus , Pogorzelski, James Stanley , Solie, Darryl Wayne
IPC分类号： H04L12/00
摘要： A terminal communications network that provides communication through a bus interface circuit to a network bus in accordance with the predetermined communications procedure, the terminal communications circuit (100) including a communications interchange circuit (132) that exchanges protocol signals with the bus interface circuit in response to commands received from a signal state controller that is resident in the terminal. The communications interchange circuit (132) further provides communications state change information to the signal state controller to indicate the contents of the protocol signals from the bus information circuit. The signal state controller executes one of a plurality of program states to control communications over the network bus in accordance with predetermined communications procedure by providing commands to the communications interchange circuit in accordance with the program state that the signal state controller is currently executing. The signal state controller changes the program state in response to the communications state change information from the communications interchange circuit. Also provided is a single command from the signal state controller to the communications interchange circuit that results in the communications interchange circuit providing a multiple of individual protocol signal patterns to the bus interface circuit enabling multiple communications procedures to be performed on the communications network with a single command from the signal state controller.
摘要翻译： 一种终端通信网络，其根据预定的通信过程通过总线接口电路向网络总线提供通信，所述终端通信电路（100）包括响应于所述总线接口电路交换协议信号的通信交换电路（132） 从驻留在终端中的信号状态控制器接收到的命令。 通信交换电路（132）还向信号状态控制器提供通信状态改变信息，以从总线信息电路指示协议信号的内容。 信号状态控制器根据预定的通信过程，通过根据信号状态控制器当前正在执行的程序状态向通信交换电路提供命令，执行多个程序状态中的一个程序状态来控制通过网络总线的通信。 信号状态控制器响应于来自通信交换电路的通信状态改变信息而改变编程状态。 还提供了从信号状态控制器到通信交换电路的单一命令，其导致通信交换电路向总线接口电路提供单个协议信号模式的多个，使得能够在通信网络上执行多个通信过程，其中单个 来自信号状态控制器的命令。
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公开(公告)号：EP0260459B1
公开(公告)日：1993-11-10
申请号：EP87111960.8
申请日：1987-08-18
发明人： Freeman, William Andrew , Wilson, Jacqueline Hegedus , Pogorzelski, James Stanley , Solie, Darryl Wayne
IPC分类号： H04L12/00
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公开(公告)号：EP0248989B1
公开(公告)日：1993-06-02
申请号：EP87104573.8
申请日：1987-03-27
IPC分类号： G06F7/02
CPC分类号： G06F7/02 , G06F2207/025
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公开(公告)号：EP0248989A2
公开(公告)日：1987-12-16
申请号：EP87104573.8
申请日：1987-03-27
IPC分类号： G06F7/02
CPC分类号： G06F7/02 , G06F2207/025
摘要： A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage (39) having combinational logic connected to receive the input signals and providing the logically combined bits to latches (34,46,50,58) of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage (63) that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter (70). The output of the counter is decoded to provide a signal when the counter counts to the specified number of bits in the predefined bit patterns.
摘要翻译： 一种通信位模式检测电路，其针对多个输入信号的一系列指定数量的位发生几个预定义位模式中的一个，以提供输出信号，其中每个输入信号是串行位数据的连续流。 通信位模式检测电路包括具有组合逻辑的检测级（39），用于接收输入信号，并将逻辑组合位提供给移位寄存器的锁存器（34,46,50,58）。 移位寄存器中的锁存器数量小于预定义位模式的指定位数。 这些锁存器的输出被提供给包括提供非检测信号的附加组合逻辑的逻辑级（63）。 该非检测信号被提供以指示所接收的比特不是任何预定义比特模式的一部分。 输入非检测信号以复位计数器（70）。 当计数器计数到预定义位模式中指定位数时，计数器的输出被解码以提供信号。
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公开(公告)号：EP0260459A3
公开(公告)日：1990-11-07
申请号：EP87111960.8
申请日：1987-08-18
发明人： Freeman, William Andrew , Wilson, Jacqueline Hegedus , Pogorzelski, James Stanley , Solie, Darryl Wayne
IPC分类号： H04L12/00
摘要： A terminal communications network that provides communication through a bus interface circuit to a network bus in accordance with the predetermined communications procedure, the terminal communications circuit (100) including a communications interchange circuit (132) that exchanges protocol signals with the bus interface circuit in response to commands received from a signal state controller that is resident in the terminal. The communications interchange circuit (132) further provides communications state change information to the signal state controller to indicate the contents of the protocol signals from the bus information circuit. The signal state controller executes one of a plurality of program states to control communications over the network bus in accordance with predetermined communications procedure by providing commands to the communications interchange circuit in accordance with the program state that the signal state controller is currently executing. The signal state controller changes the program state in response to the communications state change information from the communications interchange circuit. Also provided is a single command from the signal state controller to the communications interchange circuit that results in the communications interchange circuit providing a multiple of individual protocol signal patterns to the bus interface circuit enabling multiple communications procedures to be performed on the communications network with a single command from the signal state controller.
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公开(公告)号：EP0248989A3
公开(公告)日：1990-07-04
申请号：EP87104573.8
申请日：1987-03-27
IPC分类号： G06F7/02
CPC分类号： G06F7/02 , G06F2207/025
摘要： A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage (39) having combinational logic connected to receive the input signals and providing the logically combined bits to latches (34,46,50,58) of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage (63) that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter (70). The output of the counter is decoded to provide a signal when the counter counts to the specified number of bits in the predefined bit patterns.
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