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1.发明公开Control for enabling flight timing of hammers during printing 失效FuckzeitüberwachungderHämmerwährenddes Druckens。
公开(公告)号：EP0303124A1
公开(公告)日：1989-02-15
申请号：EP88112330.1
申请日：1988-07-29
CPC分类号： B41J9/46
摘要： A printer control apparatus provides a control circuit arrangement which enables flight timing to be performed during printing. Basically, this is achieved by providing flight time control means activated by a print hammer operation signal. Preferably the control temporarily inhibits the continuation of print hammer operation. Preferably the control inhibits print hammer operation subsequent to a selected print hammer by inhibiting the comparisons of print line and type element data contained in storage devices of the print control. Inhibiting may be for a fixed interval based on an average of the flight times of all the hammers. Alternatively the inhibiting interval may be varied according to the individual flight times of the hammers.
摘要翻译： 打印机控制装置提供了一种能够在打印期间执行飞行定时的控制电路装置。 基本上，这是通过提供由打印锤操作信号激活的飞行时间控制装置来实现的。 优选地，控制暂时禁止打印锤操作的继续。 优选地，该控制通过禁止打印线和包含在打印控制的存储装置中的类型元素数据的比较来禁止所选打印锤之后的打印锤操作。 基于所有锤子的飞行时间的平均值，抑制可以是固定的间隔。 或者，抑制间隔可以根据锤的各个飞行时间而变化。
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2.发明公开Control system for limiting the number of simultaneously activated print hammers 失效用于限制同时激活的打印机的数量的控制系统
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公开(公告)号：EP0098375B1
公开(公告)日：1988-04-20
申请号：EP83104954.9
申请日：1983-05-19
发明人： Carrington, James Edward , Hryck, Michael David , Skinner, Dean William , Westcott, Gerald Ralph
IPC分类号： G06K15/08
CPC分类号： G06K15/08
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公开(公告)号：EP0098375A2
公开(公告)日：1984-01-18
申请号：EP83104954.9
申请日：1983-05-19
发明人： Carrington, James Edward , Hryck, Michael David , Skinner, Dean William , Westcott, Gerald Ralph
IPC分类号： G06K15/08
CPC分类号： G06K15/08
摘要： @ The control system for a line printer includes compensation circuit means (29) for electronically changing the timing of the reference or home pulse to compensate for changes in the speed of the type characters (16) on a continuous type carrier (10).,The compensation circuit includes a storage register, a counter and a comparison circuit for comparing the content of the storage register and the counter. The counter when activated by a reference pulse generated from a reference mark on the moving type carrier (10) counts subscan pulses generated from timing marks moving with the type characters. The storage register, which is programmable, stores different numeric values dependent on the speed of the type carrier representing different numbers of subscan pulses to be counted by the counter means. The comparator circuit compares the numeric value in the register with the count registered in the counting means. When an equality is detected, the comparator circuit generates a modified reference or sync pulse which is applied to sync control circuitry (41) which checks the character signal produced by the type position circuitry of the printer controls.
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5.发明授权
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公开(公告)号：EP0098375A3
公开(公告)日：1985-07-03
申请号：EP83104954
申请日：1983-05-19
发明人： Carrington, James Edward , Hryck, Michael David , Skinner, Dean William , Westcott, Gerald Ralph
IPC分类号： G06K15/08
CPC分类号： G06K15/08
摘要： @ The control system for a line printer includes compensation circuit means (29) for electronically changing the timing of the reference or home pulse to compensate for changes in the speed of the type characters (16) on a continuous type carrier (10).,The compensation circuit includes a storage register, a counter and a comparison circuit for comparing the content of the storage register and the counter. The counter when activated by a reference pulse generated from a reference mark on the moving type carrier (10) counts subscan pulses generated from timing marks moving with the type characters. The storage register, which is programmable, stores different numeric values dependent on the speed of the type carrier representing different numbers of subscan pulses to be counted by the counter means. The comparator circuit compares the numeric value in the register with the count registered in the counting means. When an equality is detected, the comparator circuit generates a modified reference or sync pulse which is applied to sync control circuitry (41) which checks the character signal produced by the type position circuitry of the printer controls.
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7.发明公开Control system for a line printer having an endless type carrier 失效Steuersystemfüreinen Zeilendrucker mit einem endlosenTypenträger。
公开(公告)号：EP0114948A1
公开(公告)日：1984-08-08
申请号：EP83110957.4
申请日：1983-11-03
IPC分类号： G06K15/08
CPC分类号： G06K15/08
摘要： @ This control system for a multispeed/multipitch line printer basically comprises two read/write memories called the Band Image Buffer (19) and the Print Line Buffer (17). The Band Image Buffer (19) is loaded with the character image of the print band or chain (10) and can be visualized as an electronic band running in synchronism with the type carrier (10). The Print Line Buffer (17) is loaded with a line of data to be printed. Both buffers (17, 19) are read during each option time of a print subscan, their contents are compared in a comparator (47)-which controls the hammer firing circuits (51, 53)-, and their respective address registers (23, 22) are modified to a new value at the end of each subscan. A control bit is stored in a check buffer (20) to detect the end of each subscan. Comparison of the contents of the Band Image and Print Line Buffers (19, 17) continues until the control bit is detected signifying that a Band image Buffer correction cycle followed by a Print Line Buffer correction cycle should be performed.
摘要翻译： 用于多速/多行线路打印机的该控制系统基本上包括称为频带图像缓冲器（19）和打印行缓冲器（17）的两个读/写存储器。 带图像缓冲器（19）装载有打印带或链（10）的字符图像，并且可以被视为与类型载体（10）同步运行的电子频带。 打印行缓冲器（17）装载要打印的一行数据。 在打印副扫描的每个选择时间期间读取两个缓冲器（17,19），其内容在比较器（47）中进行比较，比较器（47） - 它控制锤击器电路（51,53），以及它们各自的地址寄存器 22）在每个副标题的末尾修改为新值。 控制位存储在检查缓冲器（20）中以检测每个副扫描的结束。 频带图像和打印线缓冲器（19,17）的内容的比较继续进行，直到检测到控制位，表示应该执行带图像缓冲区校正周期，之后是打印行缓冲区校正周期。
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8.发明公开
公开(公告)号：EP0380926A3
公开(公告)日：1992-03-18
申请号：EP90100331.9
申请日：1990-01-09
CPC分类号： G06F15/167 , G06F13/1663
摘要： A system of arbitration for access to a common memory by two asynchronous microprocessors without excluding either microprocessor for more than a predetermined, limited period of time. Two asynchronous microprocessors are connected to a common memory through an arbitration controller with a connection to transmit a "not ready" signal to one microprocessor requesting access when the other is in the process of accessing the common memory. A flip flop is connected to generate a predetermined signal output when a microprocessor requires access to the common memory, and this predetermined signal initiates a shift register to provide the internal timing of the asynchronous microprocessor requiring such access to bring it into synchronism with the clock controlling the internal cycle of the common memory. When there is contention for access to the common memory, a flip flop connects one microprocessor to the common memory, where such connection is maintained only for a predetermined, limited period of time, when access is returned to the first microprocessor. Access to the common memory by any microprocessor is always for only this one, predetermined, limited period of time.
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9.发明公开Asynchronous microprocessor random access memory arbitration controller 失效Arbitrierungssteuerungsvorrichtung为随机存取异步微处理器。
公开(公告)号：EP0380926A2
公开(公告)日：1990-08-08
申请号：EP90100331.9
申请日：1990-01-09
CPC分类号： G06F15/167 , G06F13/1663
摘要： A system of arbitration for access to a common memory by two asynchronous microprocessors without excluding either microprocessor for more than a predetermined, limited period of time. Two asynchronous microprocessors are connected to a common memory through an arbitration controller with a connection to transmit a "not ready" signal to one microprocessor requesting access when the other is in the process of accessing the common memory. A flip flop is connected to generate a predetermined signal output when a microprocessor requires access to the common memory, and this predetermined signal initiates a shift register to provide the internal timing of the asynchronous microprocessor requiring such access to bring it into synchronism with the clock controlling the internal cycle of the common memory. When there is contention for access to the common memory, a flip flop connects one microprocessor to the common memory, where such connection is maintained only for a predetermined, limited period of time, when access is returned to the first microprocessor. Access to the common memory by any microprocessor is always for only this one, predetermined, limited period of time.
摘要翻译： 仲裁用于访问由两个异步微处理器公共存储器的，但不排除任一微处理器超过预定的时间，有限的时间内更多的系统。 两个异步微处理器通过连接到一个公共存储器仲裁控制器发送“没有准备好”的信号到一个微处理器请求访问时，另一个是在访问公共存储器的进程的连接。 甲触发器被连接时的微处理器需要访问共用存储器以产生预定信号输出，并且该预定的信号发起的移位寄存器，以提供异步微处理器的要求寻求访问，使其与时钟同步控制内部定时 共用存储器的内部循环。 当出现争用访问共用存储器，触发器一个微处理器连接到公共存储器，其中寻求连接被保持为仅在预定的时间，有限的时间内，当访问被返回到第一微处理器。 通过任何微处理器访问共用存储器始终是仅此一个的，预定的时间段限制。
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