-
1.发明公开System and method for automated track follow exception monitoring 审中-公开系统和Verfahren zur automatischenÜberwachungder Spurfolgefehler
公开(公告)号：EP1083561A3
公开(公告)日：2002-11-20
申请号：EP00402385.9
申请日：2000-08-29
申请人： Iomega Corporation
发明人： Jackson, Paul , Larsen, Troy
摘要： Performance improvement during a track following operation in a disk drive is achieved by dedicating hardware to monitor specific anomalies during track following and to interrupt the processor only when specific, programmable criteria have been violated. An exemplary system comprises a servo miscue detector for checking (100) a servo sector for a miscue; a miscue counter coupled to the servo miscue detector for counting (110) a number of miscues; counter reset logic (105) coupled to the miscue counter; a comparator for comparing (115) the number of miscues to a predetermined threshold to generate an output; generate interrupt logic for generating (120) a microprocessor interrupt responsive to the output of the comparator; and a microprocessor to initiate an error recovery sequence (125) responsive to the controller. The servo miscue detector, the miscue counter, the counter reset logic, the comparator, and the generate interrupt logic are implemented in hardware.
摘要翻译： 在磁盘驱动器中的跟踪操作期间的性能改进通过专用硬件来监视跟踪期间的特定异常并且仅在违反特定的可编程标准时中断处理器来实现。 示例性系统包括用于检查（100）伺服扇区以进行误差的伺服误差检测器; 耦合到伺服误差检测器的误差计数器，用于计数（110）许多误差; 计数器复位逻辑（105）耦合到所述杂物计数器; 比较器，用于将异物数量（115）与预定阈值进行比较以产生输出; 产生响应于比较器的输出产生（120）微处理器中断的中断逻辑; 以及微处理器，用于启动响应于所述控制器的错误恢复序列（125）。 伺服误差检测器，误差计数器，计数器复位逻辑，比较器和产生中断逻辑以硬件实现。
-
公开(公告)号：EP1083561A2
公开(公告)日：2001-03-14
申请号：EP00402385.9
申请日：2000-08-29
申请人： Iomega Corporation
发明人： Jackson, Paul , Larsen, Troy
摘要： Performance improvement during a track following operation in a disk drive is achieved by dedicating hardware to monitor specific anomalies during track following and to interrupt the processor only when specific, programmable criteria have been violated. An exemplary system comprises a servo miscue detector for checking (100) a servo sector for a miscue; a miscue counter coupled to the servo miscue detector for counting (110) a number of miscues; counter reset logic (105) coupled to the miscue counter; a comparator for comparing (115) the number of miscues to a predetermined threshold to generate an output; generate interrupt logic for generating (120) a microprocessor interrupt responsive to the output of the comparator; and a microprocessor to initiate an error recovery sequence (125) responsive to the controller. The servo miscue detector, the miscue counter, the counter reset logic, the comparator, and the generate interrupt logic are implemented in hardware.
-
搜索结果
2 条记录 (耗时 0.007 秒)
