利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.009 秒)

    Semiconductor memory having redundancy memory cells
    2.
    发明公开
    Semiconductor memory having redundancy memory cells 失效
    与冗余存储单元的半导体存储器

    公开(公告)号：EP0778528A3

    公开(公告)日：2000-01-05

    申请号：EP96119623.5

    申请日：1996-12-06

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Shibata, Noboru ,  Kato, Hideo ,  Mochikuzi, Yoshio ,  Ikeda, Takafumi

    IPC分类号： G06F11/20

    CPC分类号： G11C29/80 ,  G11C29/808

    摘要： A redundancy memory cell array (12A, 12B) is arranged at an end of a main memory cell array (11A, 11B) in the column direction. Common bit lines and common column lines are arranged on the main memory cell array (11A, 11B) and the redundancy memory cell array (12A, 12B). A disconnection circuit (13A, 13B) is arranged between the main memory cell array (11A, 11B) and the redundancy memory cell array (12A, 12B) for connecting or disconnecting bit lines or column lines. A column selection switch (15A, 15B) is arranged at an end of the redundancy memory cell array (12A, 12B). A redundancy circuit (14) disconnects bit lines or column lines by means of a disconnection circuit (13A, 13B) when an address signal specifies a defective address.

    Semiconductor memory having redundancy memory cells
    3.
    发明公开
    Semiconductor memory having redundancy memory cells 失效
    Halbleiterspeicher mit redundanten Speicherzellen

    公开(公告)号：EP0778528A2

    公开(公告)日：1997-06-11

    申请号：EP96119623.5

    申请日：1996-12-06

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Shibata, Noboru ,  Kato, Hideo ,  Mochikuzi, Yoshio ,  Ikeda, Takafumi

    IPC分类号： G06F11/20

    CPC分类号： G11C29/80 ,  G11C29/808

    摘要： A redundancy memory cell array (12A, 12B) is arranged at an end of a main memory cell array (11A, 11B) in the column direction. Common bit lines and common column lines are arranged on the main memory cell array (11A, 11B) and the redundancy memory cell array (12A, 12B). A disconnection circuit (13A, 13B) is arranged between the main memory cell array (11A, 11B) and the redundancy memory cell array (12A, 12B) for connecting or disconnecting bit lines or column lines. A column selection switch (15A, 15B) is arranged at an end of the redundancy memory cell array (12A, 12B). A redundancy circuit (14) disconnects bit lines or column lines by means of a disconnection circuit (13A, 13B) when an address signal specifies a defective address.

    摘要翻译： 冗余存储单元阵列（12A，12B）被布置在列方向上的主存储单元阵列（11A，11B）的一端。 公共位线和公共列线被布置在主存储单元阵列（11A，11B）和冗余存储单元阵列（12A，12B）上。 在主存储单元阵列（11A，11B）和用于连接或断开位线或列线的冗余存储单元阵列（12A，12B）之间布置有断开电路（13A，13B）。 列选择开关（15A，15B）布置在冗余存储单元阵列（12A，12B）的一端。 当地址信号指定缺陷地址时，冗余电路（14）借助于断开电路（13A，13B）断开位线或列线。