公开(公告)号：EP1255375A4

公开(公告)日：2006-08-30

申请号：EP01961210

申请日：2001-08-30

申请人： KOYO ELECTRONICS IND CO ,  STEP TECHNICA CO LTD

发明人： MUGITANI TOMIHIRO ,  NATSUI T

IPC分类号： G06F15/17 ,  G06F1/14 ,  G06F13/00 ,  G06F15/167 ,  G06F15/177 ,  H04J3/06 ,  H04L12/28 ,  H04L12/417 ,  H04L29/06 ,  H04L7/00 ,  H04L12/40

CPC分类号： H04L12/417 ,  H04J3/0652 ,  H04L69/28

摘要： A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock (39) in each station indicates the same time and circulates from time T00 to an upper limit time TM. When the internal clock (39) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit (34) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock. If the error is out of an allowance range, the internal clock (39) is forcedly calibrated to the correct time.

摘要翻译： 一种多站存储器数据共享系统，其中通过通信线路互连的多个站之间发送/接收数据包。 每个站具有唯一的站地址值，并且时间对应于每个站地址值。 每个站内的内部时钟（39）指示相同的时间，并且从时间T00循环到上限时间TM。 当内部时钟（39）指示与站的站地址值相对应的时间时，存储在与站地址值对应的地址位置的存储器中的数据被埋入分组中，并且通过通信线路发送分组。 允许时间误差检测电路（34）比较计算出的站的内部时钟的正确时间和内部时钟指示的时间。如果误差超出允许范围，内部时钟（39）被强制校准为 正确的时间。