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公开(公告)号：EP1019794A2
公开(公告)日：2000-07-19
申请号：EP98941657.3
申请日：1998-09-24
IPC分类号： G06F1/00
CPC分类号： G06F9/30174 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G06F9/4484 , G06F9/45516 , G06F9/461
摘要： A preprocessor is functionally inserted between a memory and a processor core. The preprocessor fetches virtual machine instructions, like Java instructions, from the memory and from them it generates native instructions which are supplied to the processor core. In response to a special virtual instruction the preprocessor supplies a native jump to subroutine to the processor core, monitors when the processor core returns from that subroutine and then resumes supplying generated native instructions. The invention also provides for a processor which has a special instruction which calls a subroutine and causes the processor to convert a call context for virtual machine instructions to a call context for a high level language subroutine before making the call.
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公开(公告)号：EP0950216B1
公开(公告)日：2003-11-26
申请号：EP98940511.3
申请日：1998-09-17
IPC分类号： G06F1/00
CPC分类号： G06F9/30174 , G06F9/3861 , G06F9/3877 , G06F9/4484 , G06F9/45504 , G06F9/461
摘要： A processing device comprises an instruction memory 120 for storing virtual machine instructions, such as Java byte codes. A processor 112 of the processing device comprises a predetermined micro controller core 114 for executing native instructions from a predetermined set of micro controller specific instructions. The native instructions differ from the virtual machine instructions. The processor 112 is of a type which may request re-feeding of a plurality of native instructions. For instance, the processor 112 may have a pipeline and/or instruction cache which after an interrupt need to be re-filled. The processing device comprises a pre-processor 130 with a converter 132 for converting at least one virtual machine instruction, fetched from the instruction memory, into at least one native instruction. Feeding means 136 of the pre-processor 130 feed native instructions to the micro controller core 114 and re-feed native instructions in response to the processor requesting re-feeding of a number of native instructions. The processing device is a stack oriented machine, and at least the top elements of the stack are mapped onto registers of the processor. The position of the top of the memory stack is preferably indicated using a register of the converter.
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公开(公告)号：EP1019794B1
公开(公告)日：2008-08-20
申请号：EP98941657.3
申请日：1998-09-24
IPC分类号： G06F1/00
CPC分类号： G06F9/30174 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G06F9/4484 , G06F9/45516 , G06F9/461
摘要： A preprocessor is functionally inserted between a memory and a processor core. The preprocessor fetches virtual machine instructions, like Java instructions, from the memory and from them it generates native instructions which are supplied to the processor core. In response to a special virtual instruction the preprocessor supplies a native jump to subroutine to the processor core, monitors when the processor core returns from that subroutine and then resumes supplying generated native instructions. The invention also provides for a processor which has a special instruction which calls a subroutine and causes the processor to convert a call context for virtual machine instructions to a call context for a high level language subroutine before making the call.
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公开(公告)号：EP0950216A2
公开(公告)日：1999-10-20
申请号：EP98940511.0
申请日：1998-09-17
IPC分类号： G06F9
CPC分类号： G06F9/30174 , G06F9/3861 , G06F9/3877 , G06F9/4484 , G06F9/45504 , G06F9/461
摘要： A processing device comprises an instruction memory 120 for storing virtual machine instructions, such as Java byte codes. A processor 112 of the processing device comprises a predetermined micro controller core 114 for executing native instructions from a predetermined set of micro controller specific instructions. The native instructions differ from the virtual machine instructions. The processor 112 is of a type which may request re-feeding of a plurality of native instructions. For instance, the processor 112 may have a pipeline and/or instruction cache which after an interrupt need to be re-filled. The processing device comprises a pre-processor 130 with a converter 132 for converting at least one virtual machine instruction, fetched from the instruction memory, into at least one native instruction. Feeding means 136 of the pre-processor 130 feed native instructions to the micro controller core 114 and re-feed native instructions in response to the processor requesting re-feeding of a number of native instructions. The processing device is a stack oriented machine, and at least the top elements of the stack are mapped onto registers of the processor. The position of the top of the memory stack is preferably indicated using a register of the converter.
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5.发明公开A DEVICE FOR ACCELERATING THE INTERPRETATION OF A PROGRAM WRITTEN IN AN INTERPRETED LANGUAGE 审中-公开DEVICE - 加快解释了在解释型语言编写的程序
公开(公告)号：EP1485803A1
公开(公告)日：2004-12-15
申请号：EP03706807.9
申请日：2003-03-03
CPC分类号： G06F9/45508
摘要： The present invention relates to a device (10) for accelerating the interpretation of a program in interpreted language, said program comprising an intermediate code which can be executed by a virtual machine in the form of successive tasks, said device comprising routing means (13) able to extract a current intermediate code from a memory (11) in order to load it into storage means (16). When there is a request for a change of task, the routing means (13) are able to inhibit the extraction of the current intermediate code and to load into the storage means (16) a reserved intermediate code intended to effect a saving of a context of the virtual machine.
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