公开(公告)号：EP3506512A1

公开(公告)日：2019-07-03

申请号：EP18215835.2

申请日：2018-12-24

申请人： Lattice Semiconductor Corporation

发明人： ZHANG, Fulong ,  HANDS, Gordon ,  SINGH, Satwant ,  HAN, Wei ,  LALL, Ravindar ,  COPLEN, Joel ,  HEGADE, Sreepada ,  DING, Ming Hui

IPC分类号： H03K19/177

摘要： Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD (200). The PLD includes an array of configuration memory cells including logic block memory cells (not shown with 225) and input/output (I/O) block memory cells (not shown with 205, 210, 215, 220) associated with the PLD's logic fabric (225) and I/O fabric (25, 210, 215, 220), respectively. The method further includes programming a subset of the I/O block memory cells (205, 210) with the configuration data, and providing a wakeup signal (245out) to activate functionality associated with a portion of the I/O fabric (205, 210). The method further includes programming remaining configuration memory cells of the array (215, 220, 225) with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells (215, 220). The method further includes providing a wakeup signal (245out) to activate functionality associated with at least a portion of the logic fabric (225). Related systems and devices (230) are provided.