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1.发明公开IC CARD, DATA TRANSFER DEVICE, DATA TRANSFER METHOD, AND DATA TRANSFER METHOD PROGRAM 有权芝加哥，日内瓦，日内瓦，日内瓦，日内瓦
公开(公告)号：EP1553501A1
公开(公告)日：2005-07-13
申请号：EP03754108.3
申请日：2003-10-14
CPC分类号： G06K7/10297 , G06K7/0008 , G06K19/0723 , H04N5/4401 , H04N5/50 , H04N21/4183
摘要： An IC card capable of a high-speed data transmission to/from a data transmission apparatus which is low in processing capability, is provided. The IC card of the present invention comprises: a controlling section which generates a data packet by adding management information including information regarding a data length of the data packet, and which divides the above-mentioned data packet to generate data blocks wherein a data length of the data block is designated from the data transmission apparatus; and a communicating section which sends an interrupt signal to the above-mentioned data transmission apparatus when the above-mentioned data block which includes the above-mentioned management information is to be sent, and does not send the above-mentioned interrupt signal to the above-mentioned data transmission apparatus when a data block which does not include the above-mentioned management information is to be sent, in a case where a plurality of the above-mentioned data blocks which compose the single above-mentioned data packet are sent to the above-mentioned data transmission apparatus.
摘要翻译： 提供能够对处理能力低的数据传输装置进行高速数据传输的IC卡。 本发明的IC卡包括：控制部分，通过添加包括关于数据分组的数据长度的信息的管理信息来生成数据分组，并且将上述数据分组划分以生成数据块，其中数据长度为 从数据发送装置指定数据块; 以及当包含上述管理信息的上述数据块要发送时，向上述数据传输装置发送中断信号的通信部分，并且不向上述发送上述中断信号 在将不包含上述管理信息的数据块发送到上述数据分组的多个上述数据块的情况下，发送上述数据发送装置 上述数据发送装置。
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公开(公告)号：EP1420345A1
公开(公告)日：2004-05-19
申请号：EP02762797.5
申请日：2002-08-16
CPC分类号： G06F12/0246
摘要： To provide a nonvolatile storage device and control method thereof which improve convenience of portable devices by shortening initialization time.
In generating a data validity table at initialization, a control part firstly reads out a validity flag and a second translation table. In the case where the validity flag is valid, logical blocks in the second translation table are valid. For that reason, the fourth table generation means can set all logical blocks in the second translation table as being valid, in the data validity table. In a single reading as mentioned above, the fourth table generation means can carry out setting with respect to a plurality of logical blocks. Further, with respect to a partial logical block which is set as being valid in the data validity table, it is possible to bypass reading out the data validity flag of the block and proceed to operation of next partial logical block.摘要翻译： 提供一种通过缩短初始化时间来提高便携式设备便利性的非易失性存储设备及其控制方法。 在初始化时生成数据有效性表格时，控制部分首先读出有效性标记和第二翻译表格。 在有效标志有效的情况下，第二翻译表中的逻辑块有效。 为此，第四表生成装置可以在数据有效性表中将第二转换表中的所有逻辑块设置为有效。 在如上所述的单个读取中，第四表生成装置可以对多个逻辑块进行设置。 此外，关于在数据有效性表中被设置为有效的部分逻辑块，可以绕过读出块的数据有效性标记并且继续进行下一个部分逻辑块的操作。
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3.发明公开SEMICONDUCTOR MEMORY CARD, SEMICONDUCTOR MEMORY CONTROL APPARATUS, AND SEMICONDUCTOR MEMORY CONTROL METHOD 审中-公开HALBLEITERSPEICHERKARTE，HALBLEITERSPEICHERSTEUERVORRICHTUNG UND HALBLEITERSPEICHERSTEUERVERFAHREN
公开(公告)号：EP1667014A1
公开(公告)日：2006-06-07
申请号：EP04773322.5
申请日：2004-09-13
发明人： MAEDA, Takuji , INOUE, Shinji , GOTOH, Yoshiho , OHARA, Jun , NAKANISHI, Masahiro , TSUJITA, Shoichi , IZUMI, Tomoaki , KASAHARA, Tetsushi , TAMURA, Kazuaki , MATSUNO, Kiminori , HORIUCHI, Koichi , INOUE, Manabu
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/0625 , G06F3/0658 , G06F3/0659 , G06F3/0688 , Y02D10/154
摘要： A host information memory is provided in a semiconductor memory card and a data write start address and a data size supplied by an access unit are stored. A free physical area generation section determines whether or not to perform erasing of an invalid block of a nonvolatile memory when writing of data based on the data write start address and data size, and determines the number of blocks to be erased. When erasing, writing of data and erasing of invalid blocks are simultaneously performed with respect to different memory chips. Erase process of data, herewith, can be optimized and high speed access from the access unit to a semiconductor memory card can be realized.
摘要翻译： 在半导体存储卡中提供主机信息存储器，并存储由访问单元提供的数据写入起始地址和数据大小。 空闲物理区域生成部分基于数据写入开始地址和数据大小来确定在写入数据时是否执行非易失性存储器的无效块的擦除，并且确定要擦除的块的数量。 当擦除时，相对于不同的存储器芯片同时执行数据的写入和无效块的擦除。 可以优化数据的擦除处理，并且可以实现从存取单元到半导体存储卡的高速访问。
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4.发明公开SEMICONDUCTOR MEMORY CARD, AND ACCESSING DEVICE AND METHOD 有权ZUGANGSEINRICHTUNG超越FÜREINE HALBLEITER-SPEICHERKARTE
公开(公告)号：EP1653362A1
公开(公告)日：2006-05-03
申请号：EP04771414.2
申请日：2004-08-03
发明人： MAEDA, Takuji , INOUE, Shinji , GOTOH, Yoshiho , OHARA, Jun , NAKANISHI, Masahiro , TSUJITA, Shoichi , IZUMI, Tomoaki , KASAHARA, Tetsushi , TAMURA, Kazuaki , MATSUNO, Kiminori , HORIUCHI, Koichi , INOUE, Manabu , OCHI, Makoto
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0632 , G06F3/0679
摘要： A card information-storing portion is provided in a semiconductor memory card, and information relating to access performance such as access condition and access rate is held in the storing portion. Further, an access device acquires the held information from the semiconductor memory card to make it possible that the information can be used for control of a file system. This optimizes processing of the access device and the semiconductor memory card independent of differences in characteristics of semiconductor memory cards and management methods used, realizing high-rate access from the access device to a semiconductor memory card.
摘要翻译： 在半导体存储卡中设置有卡信息存储部，并且在存储部中保持与访问条件和访问速率等访问性能有关的信息。 此外，访问设备从半导体存储卡获取保持的信息，使得该信息可以用于文件系统的控制。 这优化了访问装置和半导体存储卡的处理，而与半导体存储卡的特性差异以及使用的管理方法无关，实现了从存取装置到半导体存储卡的高速率访问。
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5.发明公开HOST APPARATUS, ELECTRONIC DEVICE, AND TRANSMISSION SYSTEM CONTROL METHOD 有权HOST-VORRICHTUNG，ELEKTRONISCHE EINRICHTUNG UNDÜBERTRAGUNGSSYSTEMSTEUERVERFAHREN
公开(公告)号：EP1422628A1
公开(公告)日：2004-05-26
申请号：EP02751770.5
申请日：2002-07-29
IPC分类号： G06F13/362
CPC分类号： G06F13/26 , G06F13/362
摘要： To provide a method for controlling a transmission system with quick response in which plural electronic devices are connected to one host apparatus through a common data line. The method for controlling the transmission system of the present invention comprises: a step of transmitting a command signal for releasing the data line and suspending the processing through a command signal line to the electronic device occupying the data line in the state where one of the plural electronic devices is executing the processing that occupies the data line so as to make the electronic device release the data line and suspend the processing and to perform data transmission between the host apparatus and the other one of the electronic devices; and a step of resuming the suspended processing after the data transmission between the host apparatus and the other electronic device.
摘要翻译： 提供一种用于通过公共数据线将多个电子设备连接到一个主机设备的具有快速响应的传输系统的控制方法。 本发明的传输系统的控制方法包括以下步骤：发送用于释放数据线的命令信号，并通过命令信号线将处理暂停到占用数据线的电子设备， 电子设备正在执行占用数据线的处理，以使得电子设备释放数据线并暂停处理并在主机设备和另一个电子设备之间执行数据传输; 以及在主机设备和其他电子设备之间的数据传输之后恢复暂停处理的步骤。
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6.发明公开
公开(公告)号：EP1391827A1
公开(公告)日：2004-02-25
申请号：EP02728154.2
申请日：2002-05-24
IPC分类号： G06F13/24
摘要： A small-sized and low-cost transmission apparatus and a transmission method (having a high responsivity) capable of transmitting an interrupt signal with a small number of input/output terminals (without a dedicated line for interrupt signals) are provided. A first transmission apparatus of the present invention comprises a central processing unit for carrying out an interrupt process in response to an interrupt signal; an input/output section having at least one data line for transmitting data signals between a second transmission apparatus and the first transmission apparatus and for transmitting an interrupt signal from the second transmission apparatus to the first transmission apparatus; and an interrupt signal detecting section for detecting an interrupt signal from among signals transmitted from the second transmission apparatus via the data line.
摘要翻译： 提供能够以少量输入/输出端子（不用专用中断信号线）发送中断信号的小型且低成本传输装置和传输方法（具有高响应度）。 本发明的第一发送装置包括：中央处理单元，用于响应中断信号进行中断处理; 输入/输出部分，具有用于在第二传输设备和第一传输设备之间传输数据信号的至少一条数据线，并用于从第二传输设备向第一传输设备发送中断信号; 以及中断信号检测部分，用于经由数据线从第二传输装置发送的信号中检测中断信号。
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