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公开(公告)号：EP0357413A2
公开(公告)日：1990-03-07
申请号：EP89308803.9
申请日：1989-08-31
发明人： Ichinose, Makoto , Sato, Isao , Fukushima, Yoshihisa , Kuroki, Yuzuru Soshieru Mikami 103 , Takagi, Yuji
IPC分类号： G06F13/42
CPC分类号： G06F13/4213 , G06F13/4217
摘要： A novel data transfer control circuit is disclosed in which a comparator (16) compares an output of a data transfer request signal pulse counter (9) with an output of a full adder (15) which is made up of a counter output of data transfer acknowledgement pulses plus a predetermined number of words by which a data transfer request signal pulse is capable of leading a data transfer acknowledgement signal pulse. This comparator is used to stop transmission of a data transfer request signal when the counter output of the data transfer request signal becomes equal to a full adder output represented by a counter output of a data transfer acknowledgement pulse plus a predetermined number of words by which the data transfer request signal pulse is capable of leading the data transfer acknowledgement signal pulse thereby to control the transmission of the data transfer request signal for data transfer in synchronous mode according to SCSI specification. A comparator for comparing the counter output of a data transfer request signal pulse with a counter output of a data transfer acknowledgement signal pulse is also used in such a manner that when the counter output of the data transfer acknowledgement signal pulse becomes equal to that of the data transfer request signal pulse, the transmission of the data transfer acknowledgement signal is stopped thereby to control the transmission of a data transfer acknowledgement signal pulse, thus controlling the transmission of the data transfer acknowledgement signal at the time of data transfer in an asynchronous mode of SCSI specification. When the circuit is set to the transmitting end of data transfer acknowledgement signal, the data transfer acknowledgement signal for the last transfer byte is held true at the time of data transfer in asynchronous mode of SCSI specification, and when data transfer in synchronous mode is decided for the next data transfer, the data transfer aknowledgement signal is rendered false after completely preparing for the next data transfer, thus preventing the data misfetching for the data transfer in synchronous mode.
摘要翻译： 公开了一种新颖的数据传输控制电路，其中比较器（16）将数据传送请求信号脉冲计数器（9）的输出与全加器（15）的输出进行比较，该输出由数据传送的计数器输出 确认脉冲加上数据传送请求信号脉冲能够引导数据传送确认信号脉冲的预定数量的字。 该比较器用于当数据传送请求信号的计数器输出变为等于由数据传送确认脉冲的计数器输出加上预定数量的字的全加器输出时停止数据传送请求信号的发送， 数据传输请求信号脉冲能够引导数据传送确认信号脉冲，从而根据SCSI规范控制数据传输请求信号的数据传输，以同步模式进行数据传输。 用于将数据传送请求信号脉冲的计数器输出与数据传送确认信号脉冲的计数器输出进行比较的比较器也被使用，使得当数据传送确认信号脉冲的计数器输出变为等于 数据传送请求信号脉冲，数据传送确认信号的发送被停止，从而控制数据传送确认信号脉冲的发送，从而控制数据传送确认信号在异步模式下的数据传送时的传输 SCSI规范。 当电路设置为数据传送确认信号的发送端时，最后传输字节的数据传送确认信号在SCSI规范的异步模式下的数据传输时保持为真，并且当同步模式下的数据传输被决定时 对于下一次数据传输，在完成下一次数据传输准备之后，数据传送确认信号变为假，从而防止数据在同步模式下的数据传输异常。
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公开(公告)号：EP0357413B1
公开(公告)日：1996-10-23
申请号：EP89308803.9
申请日：1989-08-31
发明人： Ichinose, Makoto , Sato, Isao , Fukushima, Yoshihisa , Kuroki, Yuzuru Soshieru Mikami 103 , Takagi, Yuji
IPC分类号： G06F13/42
CPC分类号： G06F13/4213 , G06F13/4217
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公开(公告)号：EP0064196A1
公开(公告)日：1982-11-10
申请号：EP82103219.0
申请日：1982-04-16
发明人： Sato, Isao , Yoshida, Tomio , Ohara, Shunji , Koishi, Kenji
CPC分类号： G11B20/1217 , G11B7/00745 , G11B7/013 , G11B17/005 , G11B20/1419 , G11B20/1426 , G11B27/19 , G11B27/3027 , G11B2020/10888 , G11B2220/2537
摘要： A modulation and demodulation system for an optical data recording and reproducing apparatus is disclosed in which, in an optical disc (1) having an optical guide track (2) and capable of recording and reproducing optically, the guide track is divided into a plurality of data sectors (S l - S 10 ) and the recording or reproduction or reading is effected by data sector. The modulation system for the data field (8) for recording the data is different from that for the identification field (7) containing identification data (7b) such as a track address and a sector address in such a way that the identification field (7) is reproduced at high reliability and high demodulation speed while at the same time recording data at high density in the data field (8).
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公开(公告)号：EP0357413A3
公开(公告)日：1991-12-04
申请号：EP89308803.9
申请日：1989-08-31
发明人： Ichinose, Makoto , Sato, Isao , Fukushima, Yoshihisa , Kuroki, Yuzuru Soshieru Mikami 103 , Takagi, Yuji
IPC分类号： G06F13/42
CPC分类号： G06F13/4213 , G06F13/4217
摘要： A novel data transfer control circuit is disclosed in which a comparator (16) compares an output of a data transfer request signal pulse counter (9) with an output of a full adder (15) which is made up of a counter output of data transfer acknowledgement pulses plus a predetermined number of words by which a data transfer request signal pulse is capable of leading a data transfer acknowledgement signal pulse. This comparator is used to stop transmission of a data transfer request signal when the counter output of the data transfer request signal becomes equal to a full adder output represented by a counter output of a data transfer acknowledgement pulse plus a predetermined number of words by which the data transfer request signal pulse is capable of leading the data transfer acknowledgement signal pulse thereby to control the transmission of the data transfer request signal for data transfer in synchronous mode according to SCSI specification. A comparator for comparing the counter output of a data transfer request signal pulse with a counter output of a data transfer acknowledgement signal pulse is also used in such a manner that when the counter output of the data transfer acknowledgement signal pulse becomes equal to that of the data transfer request signal pulse, the transmission of the data transfer acknowledgement signal is stopped thereby to control the transmission of a data transfer acknowledgement signal pulse, thus controlling the transmission of the data transfer acknowledgement signal at the time of data transfer in an asynchronous mode of SCSI specification. When the circuit is set to the transmitting end of data transfer acknowledgement signal, the data transfer acknowledgement signal for the last transfer byte is held true at the time of data transfer in asynchronous mode of SCSI specification, and when data transfer in synchronous mode is decided for the next data transfer, the data transfer aknowledgement signal is rendered false after completely preparing for the next data transfer, thus preventing the data misfetching for the data transfer in synchronous mode.
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公开(公告)号：EP0064196B1
公开(公告)日：1986-07-23
申请号：EP82103219.0
申请日：1982-04-16
发明人： Sato, Isao , Yoshida, Tomio , Ohara, Shunji , Koishi, Kenji
CPC分类号： G11B20/1217 , G11B7/00745 , G11B7/013 , G11B17/005 , G11B20/1419 , G11B20/1426 , G11B27/19 , G11B27/3027 , G11B2020/10888 , G11B2220/2537
摘要： A modulation and demodulation system for an optical data recording and reproducing apparatus is disclosed in which, in an optical disc having an optical guide track and capable of recording and reproducing optically, the guide track is divided into a plurality of data sectors and the recording or reproduction or reading is effected by data sector. The modulation system for the data field for recording the data is different from that for the identification field containing identification data such as a track address and a sector address in such a way that the identification field is reproduced at high reliability and high demodulation speed while at the same time recording data at high density in the data field.
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