公开(公告)号：EP0772912B1

公开(公告)日：1998-05-27

申请号：EP95929688.0

申请日：1995-07-20

申请人： MITEL CORPORATION

发明人： WIECZORKIEWICZ, Jerzy ,  SHETTY, Krishna ,  KENNEY, Terry ,  VAN DER VALK, Robert, L. ,  SPIJKER, Menno, T.

IPC分类号： H03L7/099 ,  H03L7/081 ,  G06F1/02

CPC分类号： H03L7/081

公开(公告)号：EP0772912A2

公开(公告)日：1997-05-14

申请号：EP95929688.0

申请日：1995-07-20

申请人： MITEL CORPORATION

发明人： WIECZORKIEWICZ, Jerzy ,  SHETTY, Krishna ,  KENNEY, Terry ,  VAN DER VALK, Robert, L. ,  SPIJKER, Menno, T.

IPC分类号： H03L7

CPC分类号： H03L7/081

摘要： A digital phase locked loop is for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop comprises a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.